JP6264015B2 - THIN FILM TRANSISTOR AND METHOD FOR PRODUCING THIN FILM TRANSISTOR - Google Patents

Description

  The present invention relates to a thin film transistor having an In—Ga—Zn—O-based amorphous semiconductor as a channel layer.

Currently, field effect transistors are widely used as semiconductor memory integrated circuits, high-frequency signal amplifiers, and the like. Among them, a thin film transistor (TFT) is used as a switching element of a flat and thin image display device (FPD) such as a liquid crystal display device (LCD) and an organic EL electroluminescence display device (OLED). A TFT used for FPD uses an amorphous silicon thin film or a polycrystalline silicon thin film as a channel layer on a glass substrate. However, the former has a small field effect mobility of less than 1 cm ² / V · sec. The latter has drawbacks such as requiring a relatively high temperature heat step, although the field effect mobility is large.

On the other hand, in recent years, a thin film transistor using an In—Ga—Zn—O-based (hereinafter referred to as IGZO) amorphous semiconductor as a channel layer has been actively developed (for example, Non-Patent Document 1). Although this semiconductor is amorphous, its field-effect mobility may reach 10 cm ² / V · sec, and it is a highly anticipated semiconductor device in the future.

  In the TFT having the amorphous IGZO film, optimization of the threshold voltage is a big problem. In order to overcome this problem, it is an effective method to heat-treat the amorphous IGZO film. For example, improvements in threshold voltage and subthreshold value due to dry or wet oxygen atmosphere after formation of the IGZO film have been reported (for example, Non-Patent Document 2). Further, as a method for controlling the threshold voltage at a temperature lower than usual, improvement of the threshold voltage by ozone treatment of the IGZO film has been reported (for example, Patent Document 1).

JP 2011-216574 A JP 2007-299913 A

K. Nomura et al, Nature 488 (2004) 432 K. Nomura et al Appl. Phys. Lett. 93 (2008) 192107

  As described above, besides that, many studies and inventions have been made to improve thin film transistor characteristics such as field effect mobility, improvement of subthreshold value, optimization of threshold voltage, etc. Yes.

When the structure of the thin film transistor is a bottom gate type as in the case of amorphous silicon, in an actual device, a protective layer is often provided on the upper surface of the amorphous IGZO film. However, the protective layer used in the present invention includes an etching stopper layer and the like in addition to a normal protective layer. This protective layer is often SiO ₂ made by plasma CVD.

However, when the SiO ₂ film made by plasma CVD is used as a protective layer, since the passivation property is insufficient, hydrogen from the atmosphere passes through the protective film and is taken into the IGZO film, so that the threshold voltage is depleted. It has disadvantages such as shifting to the side.

  The present invention has been made in view of the above circumstances, and includes a substrate, a gate electrode, a gate insulator, an In—Ga—Zn—O-based semiconductor layer constituting a channel layer, and protection for covering the semiconductor layer. A bottom-gate thin film transistor including a layer, wherein a rare earth hydride layer serving as an insulating film is provided by capturing hydrogen over the protective layer. The layer is characterized by a layer that emphasizes the optimization and adjustment of the threshold voltage.

  The form of the thin film transistor according to claim 1 of the present invention is as follows as shown in FIG. A gate electrode 2, a gate insulating layer 4 formed on the gate electrode 2 so as to cover the gate electrode 2, a semiconductor layer 5 on the gate insulating layer 4, and a source connected to the semiconductor layer 5 This is a bottom gate / top contact type thin film transistor including an electrode 8 and a drain electrode 9. A protective film 6 and a lanthanoid rare earth hydride 7 excluding insulating Pm are laminated on the semiconductor layer 5 so as to divide the semiconductor layer 5 into two regions, and the source electrode 8 and the drain electrode 9 are respectively They are contacted and electrically connected in the region of the divided semiconductor layer 5. Further, the drain electrode 9 is connected to the pixel electrode 12 so as to cover a part of the lanthanoid rare earth hydride 7 excluding the insulating Pm. A capacitor electrode 3 is formed under the drain electrode 9 with the gate insulating layer 4 interposed therebetween.

In the case where the SiO ₂ film made by plasma CVD is used as the protective film 6, as described above, the protective film 6 has insufficient passivation properties, so that hydrogen from the atmosphere passes through the protective film 6 and is taken into the IGZO film. As a result, the threshold voltage shifts to the depletion side. In order to avoid such a shift to the depletion side, it is desirable to form a lanthanoid rare earth metal film on the protective film 6 excluding Pm which becomes an insulating film by hydrogenation. Therefore, it is desirable to use a vapor deposition method for the production method (film formation method) of the lanthanoid rare earth metal film excluding Pm.

Here, a method for forming a hydride film of Y (yttrium), Sc (scandium), or a lanthanoid rare earth metal will be described. On the protective film, for example, a Yb (ytterbium) film is formed by vapor deposition or the like. The surface of the Yb ingot used for this vapor deposition is oxidized in the air, but the inside is not violated. Therefore, it is desirable that the Yb ingot is filled and stored with an inert gas. A Yb film formed using such a Yb ingot as a vapor deposition source easily reacts with hydrogen and easily becomes YbH _{2 of a} hydride. Although details are omitted here, a film mainly composed of Yb is formed by vapor deposition or the like. A film mainly composed of Yb can be formed by an inexpensive manufacturing apparatus.

  An example in which the assumed threshold voltage Vth is changed by providing a lanthanoid rare earth hydride excluding Pm on the protective layer is shown. FIG. 4 is a diagram showing the characteristics of the gate voltage Vg and the source / drain current Id of a transistor when a TFT is fabricated without providing a lanthanoid rare earth hydride except Pm on the protective layer. FIG. 5 is a diagram showing the characteristics of the gate voltage Vg and source / drain current Id of a transistor when a TFT having a lanthanoid rare earth hydride except Pm on the protective layer is fabricated. Measurement is performed with the gate voltage from −20 V to +20 V, and the source voltage and drain voltage at 10 V. The former does not operate as a transistor at all. The latter exhibits good characteristics with a threshold voltage in the vicinity of 0V. This indicates that the threshold voltage can be controlled strongly depending on the lanthanoid rare earth hydride except Pm.

Schematic sectional view showing the structure of a thin film transistor in an embodiment of the present invention Schematic cross-sectional view and plan view showing a manufacturing process of a thin film transistor in an embodiment of the present invention Schematic cross-sectional view and plan view showing a manufacturing process of a thin film transistor in an embodiment of the present invention The graph which shows the Vg-Id characteristic of the thin-film transistor when the insulating layer for Vth control is not provided and the characteristic is not good The graph which shows the Vg-Id characteristic of a thin-film transistor when the characteristic which provided the insulating layer for Vth control is favorable

Hereinafter, the thin film transistor according to the present embodiment will be described in detail.
As shown in FIG. 1, a thin film transistor according to an embodiment of the present invention includes a substrate 1, a gate electrode 2 formed on the substrate 1, and a gate formed on the gate electrode 2 so as to cover the gate electrode 2. A bottom-gate / top-contact thin film transistor including an insulating layer 4, a semiconductor layer 5 on the gate insulating layer 4, and a source electrode 8 and a drain electrode 9 connected to the semiconductor layer 5. A protective film 6 and a lanthanoid rare earth hydride 7 excluding Pm are stacked on the semiconductor layer 5 so as to divide the semiconductor layer 5 into two regions, and the source electrode 8 and the drain electrode 9 are divided. They are in contact with each other in the region of the semiconductor layer 5 and are electrically connected. The drain electrode 9 is connected to the pixel electrode 12 so as to cover a part of the lanthanoid rare earth hydride 7 excluding Pm. A capacitor electrode 3 is formed under the drain electrode 9 with the gate insulating layer 4 interposed therebetween.

  Hereafter, each component of this invention is demonstrated in detail along a manufacturing process.

  As the substrate 1 according to the embodiment of the present invention, in addition to a non-alkali glass substrate and a quartz glass substrate, polymethyl methacrylate, polyacrylate, polycarbonate, polystyrene, polyethylene sulfide, polyethersulfone, polyolefin, polyethylene terephthalate, polyethylene naphthalate , Cycloolefin polymer, polyether sulfone, polyvinyl fluoride film, ethylene-tetrafluoroethylene copolymer resin, weather-resistant polypropylene, glass fiber reinforced acrylic resin film, glass fiber reinforced polycarbonate, transparent polyimide, fluororesin, cyclic polyolefin Resins can be used, but the present invention is not limited to these.

When the substrate 1 according to the embodiment of the present invention is an organic film, a gas barrier layer (not shown) for improving the durability of elements on the active matrix substrate can be formed. Examples of the gas barrier layer include aluminum oxide (Al ₂ O ₃ ), silicon oxide (SiO ₂ ), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), diamond-like carbon (DLC), and the like. However, the present invention is not limited to these. These gas barrier layers can be used by laminating two or more layers. The gas barrier layer may be formed only on one side of the substrate 1 using an organic film, or may be formed on both sides. The gas barrier layer can be formed using a vacuum deposition method, an ion plating method, a sputtering method, a laser ablation method, a plasma CVD (Chemical Vapor Deposition) method, a hot wire CVD method, or a sol-gel method. However, it is not limited to these.

  First, the gate electrode 2 and the capacitor electrode 3 and their respective wirings are formed on the substrate 1. The electrode portion and the wiring portion do not need to be clearly separated, and in the present invention, the constituent elements of each thin film transistor are particularly called electrodes. In the following description, when it is not necessary to distinguish between the electrode and the wiring, they are collectively referred to as a gate, a source, a drain, a capacitor, and the like.

  FIG. 2A is a schematic plan view at the stage where the gate and the capacitor are formed, and a schematic cross-sectional view taken along I-I ′ of the plan view. In FIG. 2A, the source electrode and the source wiring, and the capacitor electrode and the capacitor wiring are formed in an integrated stripe shape. Therefore, an array of thin film transistors can be arranged on the gate and capacitor lines.

  For each electrode (gate electrode 2, source electrode 8, drain electrode 9, capacitor electrode 3, pixel electrode 12) and each wiring according to the embodiment of the present invention, gold (Au), silver (Ag), copper (Cu ), Cobalt (Co), tantalum (Ta), molybdenum (Mo), chromium (Cr), aluminum (Al), nickel (Ni), tungsten (W), platinum (Pt), and titanium (Ti) Can be used.

Further, indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), cadmium oxide (CdO), indium cadmium oxide (CdIn ₂ O ₄ ), cadmium tin oxide (Cd ₂ SnO ₄ ), An oxide material such as zinc tin oxide (Zn ₂ SnO ₄ ) or indium zinc oxide (In—Zn—O) may be used. Moreover, what doped this impurity to the oxide material is also used suitably. For example, indium oxide doped with tin (Sn), molybdenum (Mo), titanium (Ti), tin oxide doped with antimony (Sb) or fluorine (F), zinc oxide indium, aluminum, gallium ( For example, doped with Ga). In addition, the conductive oxide material and gold (Au), silver (Ag), copper (Cu), cobalt (Co), tantalum (Ta), molybdenum (Mo), chromium (Cr), aluminum (Al), nickel A laminate of a plurality of metal thin films such as (Ni), tungsten (W), platinum (Pt), and titanium (Ti) can also be used.

  The gate, capacitor, source, drain, and pixel electrode 12 may be made of the same material, or may be made of different materials. However, in order to reduce the number of steps, it is more desirable that the gate and the capacitor, and the source and the drain are made of the same material. These wirings and electrodes can be formed by a vacuum deposition method, an ion plating method, a sputtering method, a laser ablation method, a plasma CVD method, a photo CVD method, or screen printing, letterpress printing, an ink jet method, etc. It is not limited to this, A publicly known general method can be used. Patterning can be performed, for example, by forming a protective film on a pattern forming portion using a photolithography method and removing an unnecessary portion by etching. However, this is not limited to this method, and a known general patterning method is used. Can be used.

Next, the gate insulating layer 4 is formed so as to cover the gate electrode 2. As shown in FIG. 1, the gate insulating layer 4 can be formed over the entire surface of the substrate 1. Materials used for the gate insulating layer 4 according to the embodiment of the present invention are SiO ₂ , SiNx, SiON, Al ₂ O ₃ , Ta ₂ O ₅ , Y ₂ O ₃ , HfO ₂ , HfAlO, ZrO ₂ , TiO. ₂ or the like, or polyacrylate such as PMMA (polymethyl methacrylate), PVA (polyvinyl alcohol), PS (polystyrene), transparent polyimide, polyester, epoxy, polyvinylphenol, polyvinyl alcohol, etc. It is not limited to. In order to suppress the gate leakage current, the resistivity of the insulating material of the gate insulating layer 4 is desirably 10 ¹¹ Ωcm or more, more preferably 10 ¹⁴ Ωcm or more. The gate insulating layer 4 is formed by a dry deposition method such as a vacuum deposition method, an ion plating method, a sputtering method, a laser ablation method, a plasma CVD method, a photo CVD method, a hot wire CVD method, a spin coating method, a dip coating method, a screen. A wet film forming method such as a printing method is appropriately used depending on the material. These gate insulating layers 4 may be used as a single layer or may be used by stacking two or more layers. Further, the composition may be inclined in the growth direction.

Next, as shown in FIG. 2B, the semiconductor layer 5 is formed at a position on the gate insulating layer 4 immediately above the gate electrode 2. As the semiconductor layer 5 according to the embodiment of the present invention, an In—Ga—Zn—O-based amorphous semiconductor is desirable. However, it is also possible to use an oxide semiconductor material whose main component is a metal oxide in which hydrogen may contribute to the increase or decrease of carriers in the semiconductor layer 5. For example, the oxide semiconductor material is an oxide containing one or more elements of zinc (Zn), indium (In), tin (Sn), tungsten (W), magnesium (Mg), and gallium. Examples thereof include zinc oxide (ZnO), indium oxide (In ₂ O ₃ ), indium zinc oxide (In—Zn—O), tin oxide (SnO), and tungsten oxide (WOx). The structure of these materials may be any of single crystal, polycrystal, microcrystal, mixed crystal of crystal and amorphous, nanocrystal scattered amorphous, and amorphous. These materials are formed using a method such as a CVD method, a sputtering method, a pulse laser deposition method, a vacuum evaporation method, or a sol-gel method. Examples of the sputtering method include an RF magnetron sputtering method and a DC sputtering method, and examples of the vacuum deposition include heating deposition, electron beam deposition, and ion plating, but are not limited thereto. The film thickness of the semiconductor layer 5 is preferably 20 nm or more.

Next, as shown in FIG. 2C, a layer made of the protective film 6 and the lanthanoid rare earth hydride 7 excluding Pm is formed on the entire surface of the gate insulating layer 4 and the semiconductor layer 5. For the protective film 6 according to the embodiment of the present invention, an inorganic material such as SiO ₂ , SiN _x silicon nitride, SiON, Al ₂ O ₃ can be selected. However, when an oxide semiconductor material is used as the semiconductor layer 5, It is desirable to select silicon oxide as the protective film. The lanthanoid rare earth hydride 7 excluding Pm includes crystalline RH ₃ type hydride containing lanthanoid rare earth element R excluding Pm (promethium), Eu (europium) and Yb (ytterbium), and Eu, Yb. It is desirable to select one of the hydrides of crystalline RH ₂ type (EuH ₂ , YbH ₂ ) of the lanthanoid rare earth element R. The film thickness of the lanthanoid rare earth hydride 7 excluding Pm is preferably 2 nm or more and 10 nm or less.

Since the lanthanoid rare earth hydride 7 excluding the protective film 6 and Pm does not have an electrical influence on the semiconductor layer 5 of the thin film transistor according to the present invention, its resistivity is 1 × 10 ¹¹ Ωcm or more, particularly 1 × 10 ^14. It is preferable that it is Ωcm or more. The lanthanoid rare earth hydride 7 excluding Pm is formed by appropriately using a dry film forming method such as a vacuum deposition method depending on the material. Examples of vacuum deposition include resistance heating vapor deposition, electron beam vapor deposition, and ion plating. The protective film 6 is formed by appropriately using a dry film forming method such as a vacuum vapor deposition method, an ion plating method, a sputtering method, a laser ablation method, a plasma CVD method, a photo CVD method, or the like if it is an inorganic material.

  Next, as shown in FIG. 2D, a first resist film 10 is formed on the layer to be the protective film 6 in accordance with the shape of the lanthanoid rare earth hydride 7 excluding the protective film 6 and Pm by a photolithography process. Form. As shown in FIG. 1, the lanthanoid rare earth hydride 7 excluding the protective film 6 and Pm covers the semiconductor layer 5 except for the contact portion between the source electrode 8 and the drain electrode 9, thereby forming the protective film 6. There is no particular limitation on the region to be performed, except that a part of the semiconductor layer 5 is exposed so as to divide the semiconductor layer 5 into two regions. Therefore, the first resist film 10 on the lanthanoid rare earth hydride 7 excluding Pm is also formed in the same shape as the lanthanoid rare earth hydride 7 excluding Pm. Although the channel width is determined by the width of the semiconductor layer 5, in the embodiment of the present invention, the source electrode 8 and the drain electrode 9 are formed after the lanthanoid rare earth hydride 7 excluding Pm. Is determined by the lamination width of the lanthanoid rare earth hydride 7 excluding the protective film 6 and Pm. Subsequently, as shown in FIG. 3A, the lanthanoid rare earth hydride 7 excluding the protective film 6 and Pm is etched and patterned using the first resist film 10 as a mask.

  For the first resist film 10 according to the embodiment of the present invention, a photosensitive acrylic resin, epoxy resin, polyimide, positive photoresist, or the like can be used, and the second resist film 11 described later has the same material. Can be used.

  Next, as shown in FIG. 3B, the conductive material of the wiring / electrode material that becomes the source electrode 8, the drain electrode 9, and the pixel electrode 12 is made of the gate insulating layer 4, the semiconductor layer 5, and the protective film 6. A film is formed on the entire surface of the substrate 1 on the lanthanoid rare earth hydride 7 excluding Pm, and the protective film 6 and the lanthanoid rare earth hydride 7 excluding Pm are covered.

  Next, as shown in FIG. 3C, the source electrode 8 and the drain electrode 9 are electrically connected while covering the exposed surfaces of the two semiconductor layers 5, respectively, and the source electrode 8 and the drain electrode 9 Pattern the conductive material layer so as to be connected only through the semiconductor layer 5. In the patterning process of the source electrode 8 and the drain electrode 9, a second resist film 11 having the same shape as the pattern of the source electrode 8 and the drain electrode 9 is formed on the conductive material layer formed on the entire surface of the substrate 1. The etching is performed by etching the conductive material layer using as a mask. The source electrode 8 and the drain electrode 9 are desirably patterned so as to overlap with the lanthanoid rare earth hydride 7 excluding the protective film 6 and Pm. Thereby, when the second resist film 11 described later is etched, the semiconductor layer 5 is covered with any one of the lanthanoid rare earth hydrides 7 except the source electrode 8 and the drain electrode 9 and Pm. There is no risk of being etched.

  Usually, the protective film 6 provided on the semiconductor layer 5 of the thin film transistor serves as an etch stopper when the source electrode 8 and the drain electrode 9 are patterned. When the thin film transistor is used as an active matrix substrate including the pixel electrode 12, the pixel electrode 12 and the drain electrode 9 are connected to each other through a via formed in the interlayer insulating layer. If there is a residue of the resist film 11, the connection reliability is lowered. Therefore, it is desirable to carefully remove the second resist film 11 described later. In the present invention, since the lanthanoid rare earth hydride 7 excluding the protective film 6 and Pm is formed on the semiconductor layer 5, even if the etching is performed until the second resist film 11 is completely removed, the semiconductor layer 5 Can be reliably prevented from being etched. Further, it has been reported that when the semiconductor layer 5 and an organic insulating material such as a resist are in direct contact with each other, the driving of the transistor is hindered (for example, Patent Document 2). By providing the lanthanoid rare earth hydride 7 excluding Pm and Pm, a resin such as epoxy or acrylic constituting the first resist film 10 or an interlayer insulating layer described later contacts the semiconductor layer 5. Deterioration can be prevented.

  Next, as shown in FIG. 3D, one of the first resist films 10 formed on the protective film 6 together with the removal of the second resist film 11 formed on the source electrode 8 and the drain electrode 9. Parts are also removed. As described above, since the step of removing the first resist film 10 on the protective film 6 which has been performed separately is performed together with the step of removing the second resist film 11 on the source electrode 8 and the drain electrode 9, The yield can be improved by reducing the step of removing the resist film 10.

  Depending on the etching method and etching time, the first resist film 10 may not be completely removed and may partially remain in the semiconductor layer 5. In particular, since the source electrode 8 and the drain electrode 9 are formed so as to partially overlap the first resist film 10, the portion of the first resist film 10 where the source electrode 8 and the drain electrode 9 overlap is not removed. It is likely to remain.

  When the thin film transistor of the present invention is used as an active matrix substrate used for driving a display or the like, an interlayer insulating layer for insulating the source electrode 8 and the pixel electrode 12 is formed on the substrate 1 on which the source electrode 8 and the drain electrode 9 are formed. To form. The protective film 6 can protect the semiconductor layer 5 from the influence of various film forming / coating methods when forming the interlayer insulating layer.

As the material of the interlayer insulating layer, inorganic materials such as SiO ₂ , SiNx, SiON, Al ₂ O ₃ , Ta ₂ O ₅ , Y ₂ O ₃ , HfO ₂ , HfAlO, ZrO ₂ , TiO ₂ , or PMMA (poly Polyacrylate such as methyl methacrylate), PVA (polyvinyl alcohol), PS (polystyrene), transparent polyimide, polyester, epoxy, polyvinylphenol, polyvinyl alcohol, and the like can be used, but are not limited thereto.

In order to insulate between the source wiring and the pixel electrode, the interlayer insulating layer preferably has a resistivity of 1 × 10 ¹¹ Ωcm or more, particularly 1 × 10 ¹⁴ Ωcm or more. Interlayer insulation layers are vacuum deposition, ion plating, sputtering, laser ablation, dry deposition methods such as plasma CVD, photo CVD, hot wire CVD, spin coating, dip coating, and screen printing. A wet film formation method such as a method is appropriately used depending on the material. Two or more of these interlayer insulating layers may be stacked and used. Moreover, it is good also as what inclined the composition toward the growth direction.

  Subsequently, a through hole with the pixel electrode 12 is provided in the interlayer insulating layer, a conductive material is formed on the interlayer insulating layer so as to be connected to the drain electrode 9, and is patterned into a predetermined pixel shape to form the second pixel electrode. By forming this, an active matrix substrate can be obtained.

  By laminating the image display element and the counter electrode on the active matrix substrate thus created, an image display device can be obtained. Examples of the image display element include an electrophoretic display medium (electronic paper), a liquid crystal display medium, an organic EL, an inorganic EL, and the like. As a lamination method, the active matrix substrate of the present invention and a laminate of a counter substrate, a counter electrode, and an image display element are bonded together, a method of sequentially stacking an image display element, a counter electrode, and a counter substrate on a pixel electrode, etc. The selection may be made appropriately depending on the type of image display element.

  Note that the transistor of this embodiment can be used as a switching element, a driving element, or the like of an image display device using a liquid crystal or an OLED element. Furthermore, the image display device using the transistor of this embodiment can be applied to a wide range of fields including a mobile phone display, a personal digital assistant (PDA), a computer display, an automobile information display, a TV monitor, or general lighting. . Furthermore, the transistor substrate of this embodiment can be a flexible substrate such as a plastic film, and can be applied to an IC card or an ID tag.

1 ... substrate 2 ... gate electrode (gate wiring)
3. Capacitor electrode (capacitor wiring)
4 ... Gate insulating layer 5 ... Semiconductor layer 6 ... Protective film 7 ... Lanthanoid rare earth hydride except Pm 8 ... Source electrode (source wiring)
9 ... Drain electrode 10 ... First resist film 11 ... Second resist film 12 ... Pixel electrode

Claims (8)

In a bottom-gate thin film transistor including a substrate, a gate electrode, a gate insulator, an In—Ga—Zn—O-based semiconductor layer that forms a channel layer, and a protective layer that covers the semiconductor layer,
A thin film transistor, wherein an insulating layer containing a rare earth hydride excluding insulating Pm is provided on the protective layer. 2. The thin film transistor according to claim 1, wherein the rare earth hydride excluding the insulating Pm is a crystalline RH ₃ type hydride of a lanthanoid rare earth element excluding Pm, Eu, and Yb. 2. The thin film transistor according to claim 1, wherein the rare earth hydride excluding the insulating Pm is a crystalline RH ₃ type hydride of Y or Sc. _2. The thin film transistor according to claim 1, wherein the rare earth hydride excluding the insulating Pm is Eu or Yb crystalline RH ₂ type (EuH ₂ or YbH ₂ ) hydride. A method of manufacturing a thin film transistor having a substrate, a gate electrode, a gate insulator, an In-Ga-Zn-O-based semiconductor layer constituting a channel layer, and a protective layer covering the semiconductor layer,
Forming a rare-earth element film other than Pm on the protective layer with a film-forming apparatus;
A method of manufacturing a thin film transistor, comprising a step of incorporating hydrogen from the protective layer and outside air into the rare earth element film to form an insulating layer containing an insulating rare earth hydride. 6. The thin film transistor according to claim 5, wherein in the step of forming a rare earth element film excluding Pm, a resistance heating apparatus is used as the film forming apparatus, and the rare earth element is deposited by the resistance heating apparatus. Manufacturing method. 6. The step of forming a rare earth element film excluding Pm uses an electron beam evaporation apparatus as the film forming apparatus, and deposits the rare earth element by the electron beam evaporation apparatus. Manufacturing method of the thin film transistor. 6. The step of forming a rare earth element film excluding Pm uses an ion plating apparatus as the film forming apparatus, and deposits the rare earth element by the ion plating apparatus. Manufacturing method of the thin film transistor.

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