JP2010205932A - Field effect transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a field effect transistor for securing ohmic contact between source and drain electrodes while protecting an active layer of an oxide semiconductor and suppressing variations in a threshold. <P>SOLUTION: The field effect transistor 100 includes: a gate electrode 12; an insulating layer 14 formed on the gate electrode; an oxide semiconductor layer 16 formed at a position opposite to the gate electrode across the insulating layer; a protective layer 18 that includes an oxide with Ga as a main constituent and is formed on the oxide semiconductor layer; contact layers 20A, 20B that include an amorphous oxide with In as a main constituent and are formed on the protective layer; and a source electrode 22A and a drain electrode 22B abutting on the contact layers and disposed opposingly on the contact layers. The contact layers are formed in a region where the protective layer, and the source and drain electrodes overlap in a thickness direction and the source electrode is separated from the drain electrode. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a field effect transistor.

  2. Description of the Related Art In recent years, flat and thin image display devices (Flat Panel Displays: FPD) have been put into practical use due to advances in liquid crystal and electroluminescence (EL) technologies. For example, an organic electroluminescence device using a thin film material that emits light when excited by passing an electric current (hereinafter sometimes referred to as “organic EL device”) can emit light with high luminance at a low voltage. In addition to light-emitting devices (lighting), mobile devices, personal digital assistants (PDAs), computer displays, automotive information displays, various displays such as TV monitors, etc. make devices thinner, lighter, and smaller. The power saving is expected.

These FPDs are generally field effect transistors using an amorphous silicon thin film or a polycrystalline silicon thin film provided on a glass substrate as an active layer (referred to as “thin film transistor” or “TFT” as appropriate). Driven by the active matrix circuit.
On the other hand, in order to further reduce the thickness, weight, and breakage resistance of FPDs, an attempt has been made to use a lightweight and flexible resin substrate instead of a glass substrate. However, the manufacture of a thin film transistor using the above-described silicon thin film as an active layer requires a relatively high temperature heat treatment step, and is generally difficult to form directly on a resin substrate having low heat resistance.

  An oxide semiconductor has been proposed as a semiconductor material that can replace the silicon thin film constituting the active layer. For example, an In—Ga—Zn—O-based amorphous oxide can be formed at a low temperature, and has attracted attention as a material that can be formed on a resin film at room temperature (see, for example, Patent Document 1). A thin film transistor using an In—Ga—Zn—O-based amorphous oxide as an active layer has higher mobility than a thin film transistor using amorphous silicon as an active layer. Therefore, a flexible film using an organic EL element is used. It has been studied as a thin film transistor for display.

As a thin film transistor using an oxide semiconductor as an active layer, for example, a thin film transistor having a stacked active layer in which an oxide semiconductor such as ZnO, SnO ₂ , In ₂ O ₃ , Zn ₂ SnO ₄ , and gallium oxide is stacked. It has been proposed (see Patent Document 2).

JP 2004-103957 A JP 2007-123702 A

  An object of the present invention is to provide a field effect transistor in which an active layer of an oxide semiconductor is protected, an ohmic contact with a source electrode and a drain electrode is secured, and a threshold fluctuation is suppressed.

In order to achieve the above object, the present invention provides the following field effect transistor.
<1> A gate electrode, an insulating layer formed on the gate electrode, an oxide semiconductor layer formed at a position facing the gate electrode across the insulating layer, and Ga as a main component A protective layer including an oxide and formed on the oxide semiconductor layer; a contact layer including an amorphous oxide containing In as a main component and formed on the protective layer; and the contact layer And a source electrode and a drain electrode that are in contact with the contact layer and are opposed to each other, wherein the contact layer includes the protective layer, the source electrode, and the drain electrode in a thickness direction. A field effect transistor which is formed in an overlapping region and is separated between the source electrode and the drain electrode.
<2> an oxide semiconductor layer, an oxide containing Ga as a main component, a protective layer formed on the oxide semiconductor layer, an amorphous oxide containing In as a main component, A contact layer formed on the protective layer; a source electrode and a drain electrode which are in contact with and in contact with the contact layer on the contact layer; and the source electrode and the drain electrode which are integrated with each other An insulating layer formed on the gate electrode, and a gate electrode formed at a position facing the oxide semiconductor layer across the insulating layer, the contact layer including the protective layer, the source electrode, A field effect transistor which is formed in a region where the drain electrode overlaps in the thickness direction, and is separated between the source electrode and the drain electrode.
<3> The electric field according to <1> or <2>, wherein the amorphous oxide contained in the contact layer is an amorphous oxide selected from the group consisting of IZO, ITO, and In ₂ O _3. Effect transistor.
<4> The field effect transistor according to any one of <1> to <3>, wherein the oxide contained in the protective layer is gallium oxide.
<5> The field effect transistor according to any one of <1> to <4>, wherein the oxide semiconductor layer is an oxide layer containing In, Ga, and Zn.

  According to the present invention, an active layer of an oxide semiconductor is protected, an ohmic contact between the active layer and the source electrode and the drain electrode is ensured, and a field effect transistor with less threshold fluctuation is provided.

1 is a schematic configuration diagram illustrating an example (first embodiment) of a field effect transistor according to the present invention. It is the schematic which shows the area | region in which the contact layer is formed. It is the schematic which shows the area | region in which the protective layer is formed. It is a figure which shows 1 process of the manufacturing method of the field effect transistor which concerns on this invention. It is a figure which shows another process of the manufacturing method of the field effect transistor which concerns on this invention. It is a figure which shows another process of the manufacturing method of the field effect transistor which concerns on this invention. It is a figure which shows another process of the manufacturing method of the field effect transistor which concerns on this invention. It is a schematic block diagram which shows the other example (2nd Embodiment) of the field effect transistor which concerns on this invention. It is a schematic block diagram which shows the other example (3rd Embodiment) of the field effect transistor which concerns on this invention.

Prior to the completion of the present invention, the present inventor conducted the following examination and research on a field effect transistor using an oxide semiconductor layer as an active layer.
There are so-called bottom-gate and top-gate TFTs based on the position of the gate electrode. However, oxide semiconductors are weak against oxygen and moisture, and are vulnerable to plasma damage when a metal electrode is formed by sputtering. The bottom gate type is preferable.
Among bottom-gate TFTs, there are so-called bottom contact types and top contact types based on contact portions between an active layer and source and drain electrodes (referred to as “source / drain electrodes” as appropriate). The contact type is preferable in that the gate insulating layer and the active layer can be continuously formed without breaking the vacuum, and a good interface can be easily obtained.
The bottom contact type is a mode in which the source / drain electrodes are formed before the active layer and the lower surface of the active layer is in contact with the source / drain electrodes. The top contact type is the type in which the active layer is the source / drain. In this embodiment, the upper surface of the active layer is in contact with the source / drain electrodes.

  However, in the top contact type, since the source electrode and the drain electrode are formed on the active layer, plasma damage or the like when the metal film for the source electrode and the drain electrode is formed by sputtering adversely affects the active layer. End up. Therefore, after forming the active layer and before forming the electrode metal, it is conceivable to form a protective layer (intermediate layer) on the active layer with gallium oxide or the like, and then form source / drain electrodes. .

  However, since gallium oxide has a low electrical conductivity, that is, it is semi-insulating, if such a semi-insulating protective layer is on the active layer, ohmic contact properties are deteriorated. Therefore, it is conceivable to improve the ohmic contact property by forming a conductive amorphous oxide layer by IZO or the like on the semi-insulating protective layer and then forming source / drain electrodes. However, in this case, since the source / drain electrodes are in contact with the conductive amorphous oxide layer, respectively, the resistance between the source / drain electrodes is lowered, resulting in an increase in off-current and threshold fluctuation. It is liable to have an adverse effect on the operating characteristics of the TFT, for example.

As a result of repeating these studies and studies, the inventor of the present invention includes a protective layer containing an oxide containing Ga or Al as a main component and an amorphous oxide containing In as a main component in a field effect transistor. It has been found that by providing the contact layer at a specific position and shape, a high resistance between the source electrode and the drain electrode is ensured and off-current is suppressed, and threshold variation is also suppressed, and the present invention is completed. It came to.
Hereinafter, a field effect transistor according to the present invention will be described in detail with reference to the accompanying drawings.

<First Embodiment>
FIG. 1 schematically shows a configuration of a thin film transistor 100 according to the first embodiment. The thin film transistor 100 according to this embodiment is a bottom gate type top contact type, and faces the gate electrode 12 with the gate electrode 12, the insulating layer 14 formed on the gate electrode 12, and the insulating layer 14 interposed therebetween. An oxide semiconductor layer 16 formed in a position, an oxide containing Ga or Al as a main component, a protective layer 18 formed on the oxide semiconductor layer 16, and an amorphous material containing In as a main component A contact layer 20A, 20B formed on the protective layer 18 and a source electrode 22A which is in contact with the contact layers 20A, 20B and is opposed to the contact layers 20A, 20B. And a drain electrode 22B. As shown in FIGS. 1 and 2, the contact layers 20A and 20B are formed in a region where the protective layer 18, the source electrode 22A, and the drain electrode 22B overlap in the thickness direction, and the source electrode 22A, the drain electrode 22B, Are separated.

  In the thin film transistor 100 having such a structure, the protective layer 18 is formed on the oxide semiconductor layer 16 as shown in FIGS. 1 and 3, so that the oxide semiconductor layer 16 is protected from air and oxygen, Even during the manufacturing process, it is protected from plasma damage, spatter damage, and the like. Further, the protective layer 18 exists between the source electrode 22A and the drain electrode 22B. However, since the conductivity is low, the source electrode 22A and the drain electrode 22B are prevented from being energized through the protective layer 18. The

  On the other hand, since the conductive contact layers 20A and 20B are interposed in the region where the protective layer 18 and the source / drain electrodes 22A and 22B overlap in the thickness direction, ohmic contact is realized. Further, since the contact layers 20A and 20B are separated between the source electrode 22A and the drain electrode 22B, the source / drain electrodes 22A and 22B are not energized through the contact layers 20A and 20B, and the source / drain electrodes A high resistance is ensured between 22A and 22B when off. Therefore, the off-current is suppressed, and the on-current flows through the oxide semiconductor layer 16 as indicated by an arrow A in FIG. 1, and exhibits stable operating characteristics in which the threshold fluctuation is also suppressed.

Next, each configuration of the field effect transistor according to the present embodiment will be specifically described.
-Board-
As the substrate (support) 10 for supporting the field effect transistor 100, at least the surface on which the field effect transistor 100 is formed has insulating properties, and has dimensional stability, solvent resistance, workability, heat resistance, and the like. Use things. For example, when an organic EL display is manufactured as a final product, a substrate in which permeation of moisture and oxygen is suppressed is used. In the case where light is transmitted from the substrate 10 side for light emission or display, a light-transmitting substrate is used.

  As the substrate 10 satisfying the above conditions, an inorganic material such as glass or zirconia stabilized yttrium oxide (YSZ) is suitable. In addition, in order to reduce the elution ion from glass, it is preferable to use an alkali free glass. Moreover, when using soda-lime glass, it is preferable to use what gave barrier coatings, such as a silica.

  On the other hand, when it is not necessary to extract light from the substrate 10 side, for example, a metal substrate such as stainless steel, Fe, Al, Ni, Co, Cu, or an alloy thereof or a semiconductor substrate such as Si is used. An insulating film for ensuring insulation may be provided. Some metal substrates are inexpensive, and even if they are thin, they are high in strength and have a high barrier property against moisture and oxygen in the atmosphere.

  Further, a resin substrate made of an organic material may be used. For example, polyesters such as polyethylene terephthalate, polybutylene terephthalate, polyethylene naphthalate, polystyrene, polycarbonate, polyethersulfone, polyarylate, allyl diglycol carbonate, polyimide, polycycloolefin, norbornene resin, poly (chlorotrifluoroethylene), etc. Examples thereof include organic materials such as synthetic resins.

  The shape, structure, size, thickness and the like of the substrate 10 are not particularly limited and may be appropriately selected according to the purpose. In general, the shape of the substrate 10 is preferably a plate shape from the viewpoints of handleability, ease of formation of the field effect transistor 100, and the like. The structure of the substrate 10 may be a single layer structure or a laminated structure. Moreover, the board | substrate 10 may be comprised by the single member and may be comprised by two or more members.

-Gate electrode-
The gate electrode 12 controls the current between the source / drain electrodes 22A and 22B through the active layer 16 by applying a voltage. Examples of the material constituting the gate electrode 12 include metals such as Al, Mo, Cr, Ta, Ti, Au, and Ag, alloys such as Al—Nd and APC, tin oxide, zinc oxide, indium oxide, and indium oxide. Preferred examples include metal oxide conductive films such as tin (ITO) and zinc indium oxide (IZO), organic conductive compounds such as polyaniline, polythiophene, and polypyrrole, or mixtures thereof.
The thickness of the gate electrode 12 is preferably 10 nm or more from the viewpoint of reducing the resistance of the gate wiring and preventing the delay of the control signal of the TFT. From the viewpoint of preventing the above, it is preferably 1000 nm or less.

−Insulating layer−
The insulating layer (gate insulating layer) 14 is formed on the gate electrode 12. The gate insulating layer 14 is made of an insulator such as SiO ₂ , SiN _x , SiON, Al ₂ O ₃ , Y ₂ O ₃ , Ta ₂ O ₅ , HfO _{2, and the} like, and includes an insulating layer containing two or more of these compounds. It is good. Alternatively, a polymer insulator such as polyimide may be used.

  The thickness of the gate insulating layer 14 needs to have a thickness for suppressing leakage current and improving the voltage resistance. On the other hand, if the thickness of the gate insulating layer 14 is too large, the driving voltage is increased. Although depending on the material of the gate insulating layer 14, the thickness of the gate insulating layer 14 is preferably 50 nm or more and 1000 nm or less in the case of an inorganic insulator from the viewpoint of time required for film formation and voltage resistance. If it exists, 0.5 micrometer or more and 5 micrometers or less are preferable.

-Oxide semiconductor layer-
The oxide semiconductor layer (active layer) 16 is formed at a position facing the gate electrode 12 with the insulating layer 14 interposed therebetween. As a material constituting the oxide semiconductor layer 16, an amorphous oxide semiconductor is preferable. Since an amorphous oxide semiconductor can be formed at a low temperature, it can be formed over a flexible resin substrate such as plastic.
An amorphous oxide semiconductor containing at least one of In, Ga, Zn, and Sn is preferable, and an amorphous oxide semiconductor containing In or Zn is more preferable. As an amorphous oxide semiconductor that can be formed at a low temperature, an oxide containing In, an oxide containing In and Zn, and an oxide containing In, Ga, and Zn can be given. As a composition structure, InGaO ₃ (ZnO) _m (m is a natural number less than 6) is preferred. These are n-type semiconductors whose carriers are electrons. Note that a p-type oxide semiconductor such as ZnO.Rh ₂ O ₃ , CuGaO ₂ , or SrCu ₂ O ₂ may be used for the active layer 16, or an oxide semiconductor disclosed in Japanese Patent Application Laid-Open No. 2006-165529. May be used.

An amorphous oxide semiconductor whose composition in the crystalline state is represented by InGaO ₃ (ZnO) _m (m is a natural number less than 6) is preferable, and InGaZnO ₄ (referred to as “IGZO” as appropriate) is particularly preferable. As a feature of the amorphous oxide semiconductor having this composition, the electron mobility tends to increase as the electrical conductivity increases. In order to control the electrical conductivity, it can be controlled by the oxygen partial pressure during film formation.
The thickness of the oxide semiconductor layer 16 is preferably not less than 50 nm and not more than 150 nm, from the viewpoint of sufficient drain current flow and the time required for film formation to be not too long.
Further, the electrical conductivity of the oxide semiconductor layer 16 is preferably 10 ⁻⁴ Scm ⁻¹ or more and less than 10 ² Scm ⁻¹ in order to function as an active layer, and is 10 ⁻¹ Scm ⁻¹ or more and 10 ² Scm ^−. More preferably, it is less than ¹ .

-Protective layer-
The protective layer 18 includes an oxide containing Ga or Al as a main component and is formed on the oxide semiconductor layer 16. Here, the “oxide containing Ga or Al as a main component” means that the oxide constituting the protective layer 18 has the largest content (mass ratio) of Ga or Al among the constituent components other than oxygen. And it is preferable that it is 50 mass% or more, and it is more preferable that it is 90 mass% or more. Specific examples of the oxide mainly composed of Ga or Al constituting the protective layer 18 include Ga ₂ O ₃ and Al ₂ O ₃ . Alternatively, an In—Ga—Zn—O-based oxide which contains more Ga than In and Zn (preferably, Ga is 50% by mass or more) may be a Ga-rich oxide. Note that when an IGZO layer is formed as the oxide semiconductor layer 16, gallium oxide, specifically, Ga ₂ O ₃ or Ga-rich In as described above is used from the viewpoints of electrical characteristics and affinity. It is preferable to form the protective layer 18 from a —Ga—Zn—O-based oxide.

  The protective layer 18 may be formed at least in the region overlapping with the source / drain electrodes 22A and 22B and the region between the source / drain electrodes 22A and 22B on the oxide semiconductor layer 16, but the oxide semiconductor layer 16 is effective. From the viewpoint of protection, it is preferable that the oxide semiconductor layer 16 is formed over the entire surface as shown in FIG.

The thickness of the protective layer 18 is preferably 10 nm or more from the viewpoint of reliably protecting the active layer 16 from sputtering damage during the formation of the source / drain electrodes 22A and 22B and from the outside air (oxygen, moisture) after manufacture. On the other hand, since the protective layer 18 is low in conductivity, if the protective layer 18 is too thick, the insulating property becomes high and the drive voltage may increase. From the viewpoint of suppressing an increase in driving voltage, the thickness of the protective layer 18 is preferably 30 nm or less.
The electric conductivity of the protective layer 18, in order to prevent conduction between the source and drain through the protective layer 18 ^is preferably less than 10 6 ^{Scm -1} or more ^{10 12 Scm -1, 10 7 Scm} -1 More preferably, it is less than 10 ¹⁰ Scm ⁻¹ .

-Contact layer-
The contact layers 20A and 20B include an amorphous oxide containing In as a main component, and are formed in a region where the protective layer 18, the source electrode 22A, and the drain electrode 22B overlap in the thickness direction, and the source electrode 22A and the drain electrode 22B is in contact with the source electrode 22A and the drain electrode 22B. Here, the “amorphous oxide containing In as a main component” means that the oxide constituting the contact layers 20A and 20B has the largest In content (mass ratio) among the constituent components other than oxygen. It is preferably 75% by mass or more, and more preferably 80% by mass or more. In this embodiment, the contact layers 20A and 20B are also in contact with the protective layer 18. However, the contact layers 20A and 20B do not necessarily have to be in contact with the protective layer 18, and other portions are provided between the protective layer 18 and the contact layers 20A and 20B. Layer (intermediate layer) may be interposed.

As an amorphous oxide constituting the contact layers 20A and 20B, for example, when an IGZO layer is formed as the oxide semiconductor layer 16, amorphous IZO (indium zinc) is used from the viewpoint of affinity, ohmic contact property, and the like. Oxide), amorphous ITO (indium tin oxide), or amorphous In ₂ O ₃ .
The thickness of the contact layers 20A and 20B is preferably 10 nm or more from the viewpoint of reliably realizing ohmic contact, and is preferably 30 nm or less from the viewpoint of preventing the time required for film formation from becoming too long.
Further, the electrical conductivity of the contact layers 20A and 20B is preferably 10 ¹ Scm ⁻¹ or more and less than 10 ⁴ Scm ⁻¹ in order to reliably realize ohmic contact, and is 10 ² Scm ⁻¹ or more and 10 ³ Scm ^−. More preferably, it is less than ¹ .

−Source / Drain electrode−
The source electrode 22A and the drain electrode 22B are in contact with and in contact with the contact layers 20A and 20B on the contact layers 20A and 20B.
Specifically, the materials constituting the source / drain electrodes 22A and 22B include metals such as Al, Mo, Cr, Ta, Ti, Au, and Ag, alloys such as Al—Nd and APC, tin oxide, and zinc oxide. And metal oxide conductive films such as indium oxide, indium tin oxide (ITO), and zinc indium oxide (IZO), organic conductive compounds such as polyaniline, polythiophene, and polypyrrole, or a mixture thereof. Since the source / drain electrodes 22A and 22B are in contact with the contact layers 20A and 20B containing an amorphous oxide containing In as a main component, a metal, an alloy, or a metal oxide is used because of the affinity with the contact layers 20A and 20B. It is preferable to form from a physical conductive film.

  The thicknesses of the source electrode 22A and the drain electrode 22B vary depending on the material, the final product, and the like, but are preferably 10 nm or more and 1000 nm or less in consideration of film formability, conductivity (lower resistance), and the like. When the active layer is formed after the source / drain electrodes 22A and 22B, the thickness of the source / drain electrodes 22A and 22B is limited in consideration of reducing the thickness and steps of the active layer. In the embodiment, since the source / drain electrodes 22A and 22B are formed after the active layer 16 and the like are formed, the source / drain electrodes 22A and 22B are compared with the case where the active layer 16 is formed after the source / drain electrodes 22A and 22B. It is also possible to reduce the resistance by forming 22B thicker.

  Next, a method for manufacturing the thin film transistor 100 according to the present embodiment will be specifically described. 4 to 7 schematically show steps of manufacturing the thin film transistor 100 according to this embodiment.

-Formation of gate electrode-
A gate electrode 12 is formed on the substrate 10. For example, suitability for materials used from wet methods such as printing methods, coating methods, physical methods such as vacuum deposition methods, sputtering methods, ion plating methods, chemical methods such as CVD and plasma CVD methods, etc. The film is formed according to a method appropriately selected in consideration of the above.
After film formation, patterning is performed into a predetermined shape by photolithography. At this time, the gate electrode 12 and the gate wiring are simultaneously patterned.

-Formation of gate insulation layer-
After forming the gate electrode 12 on the substrate 10, an insulating layer (gate insulating layer) 14 is formed. The gate insulating layer 14 is used among wet methods such as a printing method and a coating method, a physical method such as a vacuum deposition method, a sputtering method, and an ion plating method, and a chemical method such as a CVD method and a plasma CVD method. A film is formed on the gate electrode 12 and the substrate 10 according to a method appropriately selected in consideration of suitability with the material, and is patterned into a predetermined shape by photolithography as necessary.

-Formation of oxide semiconductor layer, protective layer, and contact layer-
A method for forming the oxide semiconductor layer 16, the protective layer 18, and the contact layers 20A and 20B is not particularly limited, but the oxide semiconductor layer 16, the protective layer 18, and the contact layers 20A and 20B can be formed in a predetermined pattern by lift-off or etching using a resist.
For example, a lift-off resist is applied on the gate insulating layer 14 and developed after exposure. Here, a material that dissolves in an alkaline stripping solution is used for the lift-off resist. As a result, as shown in FIG. 4, the resist pattern 32 is formed such that the gate insulating layer 14 is exposed at the portion where the oxide semiconductor layer 16 is to be formed and the resist film is left at the portion where the oxide semiconductor layer 16 is not formed. Form.

  Next, an IGZO layer 16 is formed as an active layer. For example, deposition is performed using a vapor phase deposition method using a polycrystalline sintered body of an oxide semiconductor containing In, Ga, and Zn in a target composition as a target. Among the vapor phase film forming methods, the sputtering method and the pulse laser deposition method (PLD method) are more preferable, and the sputtering method is particularly preferable from the viewpoint of mass productivity.

After the IGZO layer 16 is formed, a Ga ₂ O ₃ layer 18 is sequentially formed as a protective layer, and an IZO layer 20 is sequentially formed as a contact layer. In this case as well, each film may be formed by sputtering using a target corresponding to each of the layers 18 and 20. As a result, as shown in FIG. 5, the IGZO layer 16, the Ga ₂ O ₃ layer 18, and the IZO layer 20 are stacked on the gate insulating layer 14 and the resist pattern 32.
In addition, each layer 16, 18, and 20 can confirm a crystal state by the X-ray diffraction method or the high-resolution cross-sectional TEM photograph, respectively. The thickness can be obtained by stylus surface shape measurement or a cross-sectional TEM photograph, and the composition ratio can be obtained by XRF (fluorescence X-ray analysis), XPS (X-ray photoelectron spectroscopy), or SIMS. it can.

After the IGZO layer 16, the Ga ₂ O ₃ layer 18, and the IZO layer 20 are sequentially formed and laminated, the resist pattern 32 is dissolved by a stripping solution (alkaline). At this time, the layers 16, 18, and 20 on the resist pattern 32 are removed together with the dissolution of the resist, but the outermost IZO layer 20 is an alkaline solution in the layers 16, 18, and 20 formed on the insulating layer 14. Since it hardly dissolves, it remains as it is.

-Formation of source / drain electrodes-
Next, source / drain electrodes 22A and 22B are formed. A method of forming the source / drain electrodes 22A and 22B is not particularly limited, but a pattern can be formed by lift-off or etching using a resist.
For example, a resist pattern 34 for lift-off is formed. Again, the lift-off resist is made of a material that dissolves in an alkaline stripping solution, coated with a resist, developed after exposure. Thereby, in the region where the source / drain electrodes 22A and 22B are to be formed, the stacked body 24 or the gate insulating layer 14 of the IGZO layer 16, the Ga ₂ O ₃ layer 18 and the IZO layer 20 is exposed, and the source electrode 22A and the drain In the region where the electrode 22B is not formed, the resist film 34 is left including the region between the source / drain electrodes 22A and 22B.

After the lift-off resist pattern 34 is formed, a metal film 22 for forming the source / drain electrodes 22A and 22B is formed as shown in FIG. The film forming method is not particularly limited, and can be selected from a printing method, a wet method such as a coating method, a physical method such as a vacuum deposition method, a sputtering method, and an ion plating method, and a chemical method such as CVD and plasma CVD method. The film may be formed according to a method selected in consideration of suitability for the material. For example, the Mo film 22 is formed by a sputtering method. Thereby, the Mo film 22 is formed on each exposed portion of the gate insulating layer 14, the stacked body 24, and the resist pattern 34.
For example, when ITO is selected as the material of the source electrode 22A and the drain electrode 22B, the film can be formed according to a direct current or high frequency sputtering method, a vacuum deposition method, an ion plating method, etc. When selecting, it can be performed according to a wet film-forming method.

  After the Mo film 22 is formed, the resist pattern 34 is dissolved and removed using a stripping solution (alkaline). As a result, as shown in FIG. 7, the Mo film 22 formed on the resist pattern 34 is removed together with the resist 34, and the Mo film 22 remains in the regions exposed from the resist pattern 34, so that the source / drain electrodes 22A and 22B are formed. Note that the IZO layer 20 is exposed between the source / drain electrodes 22A and 22B after the resist pattern 34 is removed by the stripping solution. However, because of the alkali resistance, the laminate 24 remains as it is.

On the other hand, when etching is performed as the formation of the source / drain electrodes 22A and 22B, the equipment for dry etching is expensive and the manufacturing cost increases. Therefore, processing using wet etching that can reduce the cost is desirable. For example, the protective layer 18 is a Ga ₂ O ₃ based amorphous oxide film (thickness: 10 nm or more), and the contact layer 20 is an In ₂ O ₃ based amorphous oxide film (thickness: 10 nm or more). Thus, the formation of the source / drain electrodes 22A and 22B by wet etching can be realized without affecting the oxide semiconductor layer 16.

-Partial removal of contact layer-
Next, the IZO layer 20 exposed from the source / drain electrodes 22A and 22B is removed by etching. For example, by etching using a weak acid such as oxalic acid, the exposed portion of the IZO layer 20 is dissolved and removed, and is sandwiched between the Ga ₂ O ₃ layer 18 and the source / drain electrodes 22A and 22B. The part remains. Note that the Ga ₂ O ₃ layer 18 is exposed in the portion where the IZO layer 20 is removed. The Ga ₂ O ₃ layer 18 is easily dissolved in an alkaline stripping solution, but is acid-resistant, and remains as it is for an acidic etching solution, functioning as an etching stopper. As a result, the conductive amorphous oxide IZO layer 20 is interposed only in the portion (overlap region) where the source / drain electrodes 22A and 22B and the active layer (IZO layer) 20 overlap in the thickness direction. On the entire surface, the Ga ₂ O ₃ layer 18 remains as a protective layer.

Through the steps as described above, the thin film transistor 100 having the structure shown in FIG. 1 is manufactured. TFT 100 having such a structure, with the upper surface of the IGZO layer 16 is protected from the outside air is covered with _Ga 2 _{O 3} layer 18 (oxygen, water), _Ga 2 _{O 3} layer 18 and the source and drain electrodes 22A, Since the conductive IZO layers 20A and 20B are interposed between the two layers 22B, ohmic contact is realized.

On the other hand, since the IZO layers 20A and 20B are separated between the source electrode 22A and the drain electrode 22B and are not on the back channel, the source / drain electrodes 22A and 22B cannot be energized through the IZO layers 20A and 20B. There is no adverse effect on the TFT operation.
Further, the Ga ₂ O ₃ layer 18 is formed on the entire surface of the IGZO layer 16 and exists between the source electrode 22A and the drain electrode 22B. However, since the conductivity is low, the Ga ₂ O ₃ layer 18 is present. In the off state, a high resistance is maintained between the source and drain electrodes. Therefore, the on-current is supplied to the source / drain electrodes 22A and 22B through the IGZO layer 16 as shown by the arrow A in FIG. 1, and exhibits stable operating characteristics.

  After the field effect transistor 100 is manufactured, a pixel electrode or the like may be further formed according to the final product (display device, imaging device, or the like). For example, when manufacturing an organic EL display, an interlayer insulating film, a pixel electrode, and the like are formed, and an upper electrode (common electrode) is sequentially formed using an organic electroluminescence layer and Al, and then sealed with glass or the like.

<Second Embodiment>
FIG. 8 schematically shows a configuration of a thin film transistor 200 according to the second embodiment. In the thin film transistor 200 according to this embodiment, a protective layer 18 containing an oxide containing Ga or Al as a main component is formed on the oxide semiconductor layer 16. Between the protective layer 18 and the source / drain electrodes 22A, 22B, contact layers 20A, 20B containing an amorphous oxide containing In as a main component are formed, and are in contact with the source / drain electrodes 22A, 22B. And the source electrode 22A and the drain electrode 22B are separated. Further, first intermediate layers 17A, 17B and second intermediate layers 19A, 19B are formed between the protective layer 18 and the contact layers 20A, 20B. These intermediate layers 17A, 17B, 19A, 19B are formed in regions where the oxide semiconductor layer 16 and the source / drain electrodes 22A, 22B overlap in the thickness direction, like the contact layers 20A, 20B. 22A and the drain electrode 22B are separated. Therefore, the source electrode 22A and the drain electrode 22B are not energized through these intermediate layers 17A, 17B, 19A, 19B.

In the thin film transistor 200 having such a structure, the oxide semiconductor layer 16 is covered with the protective layer 18, and thus is protected from damage during the manufacturing process and outside air. For example, in order to increase the damage prevention effect in the manufacturing process, after forming the Ga ₂ O ₃ layer 18 as a protective layer, the IZO layers 17A and 17B are interposed with a thickness of about 10 nm, and then again the Ga ₂ O ₃ layer 19A, It is effective to stack 19B with a thickness of about 10 nm.
Further, in the region where the protective layer 18 and the source / drain electrodes 22A, 22B overlap, the contact layers 20A, 20B having higher conductivity than the protective layer 18 are in contact with the source / drain electrodes 22A, 22B. Is realized. Therefore, a high resistance is secured between the source / drain electrodes 22A and 22B when off, and a current is passed between the source / drain electrodes 22A and 22B via the oxide semiconductor layer 16 as shown by an arrow A in FIG. The threshold fluctuation is suppressed, and stable operation characteristics are exhibited.

Hereinafter, examples will be described, but the present invention is not limited thereto. In the following description, the numerical value with the unit (nm) in parentheses represents the film thickness.
<Example 1>
A thin film transistor having the configuration shown in FIG. 1 was manufactured through the following steps.
A Mo film (40 nm) was formed as a gate electrode on a glass substrate by sputtering.
Next, a SiO ₂ film (200 nm) was formed as a gate insulating layer by sputtering.
In order to form an islanded active layer on the gate insulating layer opposite to the gate electrode, application of a lift-off resist (manufactured by Tokyo Ohka Kogyo Co., Ltd .: TSMR8900), pattern exposure, and development were sequentially performed.

Next, an IGZO film (50 nm) / Ga ₂ O ₃ film (10 nm) / IZO film (10 nm) were successively formed by sputtering.
Next, the lift-off resist was stripped with an alkaline stripping solution (manufactured by AZ: AZ remover 100), and then rinsed with pure water. At this time, the IZO film (10 nm) did not disappear.

In order to form a lift-off so that the source / drain electrodes partially overlap the active layer, a lift-off resist (Tokyo Ohka Kogyo Co., Ltd .: TSMR8900) was applied, exposed, and developed.
After forming a resist pattern for lift-off, a Mo film (40 nm) was formed as a solid film.
Next, the lift-off resist was stripped with an alkaline stripping solution (AZ remover 100) and rinsed with pure water. At this time, the IZO film (10 nm) did not disappear.
Further, it was immersed in oxalic acid for 5 minutes to remove the IZO film in the back channel portion.
Thus, a thin film transistor having a configuration as shown in FIG. 1 was manufactured.
The obtained thin film transistor operated satisfactorily with little off-state current and threshold fluctuation. At this time, the gate length of the thin film transistor is 200 μm, the gate width is 1000 μm, and the measurement conditions of the transistor are conditions in which a fixed voltage of 10 V is applied to the drain voltage and the gate voltage is scanned 10 times from −10 V to +15 V.

<Example 2>
A thin film transistor having the configuration shown in FIG. 8 was manufactured through the following steps.
Similarly to Example 1, a Mo film (40 nm) as a gate electrode and a SiO ₂ film (200 nm) as a gate insulating layer were sequentially formed on a glass substrate.
Application of lift-off resist, pattern exposure, and development were sequentially performed in order to form an islanded active layer on the gate insulating layer facing the gate electrode.

Next, IGZO film (50 nm) / first Ga ₂ O ₃ film (10 nm) / first IZO film (10 nm) / second Ga ₂ O ₃ film (10 nm) / second IZO film (10 nm) Continuous film formation was performed by sputtering.

In order to make the active layer into an island, a resist for wet etching (manufactured by Tokyo Ohka Kogyo Co., Ltd .: TSMR8900) was applied, patterned, and developed to form a resist mask.
Next, the active layer was etched and patterned using an Al etching solution (manufactured by Kanto Chemical Co., Inc .; mixed solution of phosphoric acid, nitric acid and acetic acid).
After the etching, the resist was stripped with an alkaline stripping solution (AZ remover 100) and rinsed with pure water. At this time, the second IZO film on the outermost surface remained.

  Next, a solid Mo film (100 nm) for source / drain electrodes was formed. In order to form the source / drain electrodes by wet etching so that a part of the source / drain electrodes overlaps the active layer, the resist was applied, exposed and developed, and then etched with an Al etching solution. The second IZO film on the outermost surface disappeared in the back channel region and remained in the overlap region.

The resist mask was stripped with an alkaline stripping solution (AZ remover 100) and rinsed with pure water. At this time, the second Ga ₂ O ₃ film in the back channel region disappeared and the first IZO film remained. The second Ga ₂ O ₃ film and the first IZO film in the overlap region remained.

In this state, the first IZO film was removed only in the back channel region by immersing in oxalic acid for 3 minutes. At this time, the second Ga ₂ O ₃ film and the first IZO film in the overlap region remained.
Thus, a thin film transistor having a configuration as shown in FIG. 8 was manufactured.
The obtained thin film transistor operated satisfactorily with little off-state current and threshold fluctuation. At this time, the gate length of the thin film transistor is 200 μm, the gate width is 1000 μm, and the measurement conditions of the transistor are conditions in which a fixed voltage of 10 V is applied to the drain voltage and the gate voltage is scanned 10 times from −10 V to +15 V.

<Comparative Example 1>
Except that the IZO film in the back channel portion was not removed, the same processing as in Example 1 was performed, so that a TFT in which the contact layers 20A and 20B were connected, that is, the TFT shown in FIG. 7 was manufactured.
In this case, drain current always flowed, and the TFT did not show off operation.

As mentioned above, although this invention was demonstrated, this invention is not limited to the said embodiment and comparative example.
For example, in the embodiment and the example, the case where the protective layer includes an oxide containing Ga as a main component (Ga ₂ O ₃ ) is mainly described, but an oxide containing Al as a main component (Al ₂ O) is mainly described. The same effect can be obtained as a protective layer containing ₃ ).

  In the embodiments and examples, the bottom-gate thin film transistor is mainly described. However, for example, a top-gate thin film transistor 300 may be used as illustrated in FIG. In this case, on the substrate 10, the oxide semiconductor layer 16, the protective layer 18 includes a protective layer 18 containing an oxide containing Ga or Al as a main component, a source electrode 22A and a drain electrode 22B, and In as a main component. Contact layers 20A and 20B containing an amorphous oxide to be formed, an insulating layer 14 integrally formed on the source electrode 22A and the drain electrode 22B, and a position facing the oxide semiconductor layer 16 with the insulating layer 14 therebetween. And a gate electrode 12 formed on the substrate. The contact layers 20A and 20B are formed between the protective layer 18, the source electrode 22A and the drain electrode 22B, are in contact with the source electrode 22A and the drain electrode 22B, and are separated between the source electrode 22A and the drain electrode 22B. is doing. Even in the top-gate thin film transistor 300 having such a configuration, the active layer 16 is protected by the protective layer 18, and the source / drain electrodes 22A and 22B are in contact with the contact layers 20A and 20B to form ohmic contacts. As a result, off-state current and threshold fluctuation are suppressed, and stable operating characteristics are exhibited.

10 Substrate 12 Gate electrode 14 Insulating layer 16 Oxide semiconductor layer (active layer)
17A, 17B First intermediate layer 18 Protective layer 19A, 19B Second intermediate layer 20A Source electrode 20B Drain electrode 22 Metal film 24 Laminate 32, 34 Resist pattern 100, 200 Field effect transistor (bottom gate type)
300 Field Effect Transistor (Top Gate Type)

Claims (5)

A gate electrode;
An insulating layer formed on the gate electrode;
An oxide semiconductor layer formed at a position facing the gate electrode across the insulating layer;
A protective layer containing an oxide containing Ga as a main component and formed on the oxide semiconductor layer;
A contact layer containing an amorphous oxide mainly composed of In and formed on the protective layer;
On the contact layer, a source electrode and a drain electrode that are in contact with the contact layer and disposed opposite to each other, and
The field effect transistor, wherein the contact layer is formed in a region where the protective layer, the source electrode, and the drain electrode overlap in a thickness direction, and the source electrode and the drain electrode are separated from each other. An oxide semiconductor layer;
A protective layer containing an oxide containing Ga as a main component and formed on the oxide semiconductor layer;
A contact layer containing an amorphous oxide mainly composed of In and formed on the protective layer;
On the contact layer, a source electrode and a drain electrode that are in contact with the contact layer and are disposed opposite to each other, and
An insulating layer integrally formed on the source electrode and the drain electrode;
A gate electrode formed at a position facing the oxide semiconductor layer with the insulating layer interposed therebetween,
The field effect transistor, wherein the contact layer is formed in a region where the protective layer, the source electrode, and the drain electrode overlap in a thickness direction, and the source electrode and the drain electrode are separated from each other. _3. The field effect transistor according to claim 1, wherein the amorphous oxide contained in the contact layer is an amorphous oxide selected from the group consisting of IZO, ITO, and In ₂ O _3. .   The field effect transistor according to any one of claims 1 to 3, wherein the oxide contained in the protective layer is gallium oxide.   The field effect transistor according to any one of claims 1 to 4, wherein the oxide semiconductor layer is an oxide layer containing In, Ga, and Zn.

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