JP2012038891A - Bottom-gate type thin film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a bottom-gate type thin film transistor with less change in shape in a sub-threshold region of a transfer characteristic.SOLUTION: A bottom-gate type thin film transistor comprises in this order on a substrate, a gate electrode layer, a gate insulation layer, and an oxide semiconductor layer in which a channel region, a source region, and a drain region are formed in one layer and the source region and the drain region are provided via the channel region. At least a part of a corner of an end part in the width direction of each of the source region and the drain region on the side closer to the channel region is positioned inward as compared with an end part of the channel region on the same side as the end part.

Description

  The present invention relates to a bottom-gate thin film transistor using an oxide semiconductor as a semiconductor layer.

  Thin film transistors (TFTs) using amorphous silicon or low-temperature polysilicon as a semiconductor layer are widely used as drive elements used for driving display elements such as active matrix liquid crystal display elements and organic electroluminescence (EL) elements. . However, a high-temperature process is indispensable for manufacturing these TFTs, and it is difficult to use a flexible substrate having low heat resistance such as a plastic substrate or a film substrate.

  Therefore, in recent years, TFTs using an oxide semiconductor as a semiconductor layer, which can be formed at a low temperature, have been actively developed. As a TFT using an oxide semiconductor for a semiconductor layer, for example, there is a TFT mainly composed of ZnO.

  In manufacturing a top gate type polycrystalline oxide TFT mainly composed of ZnO, a method of forming an interlayer insulating layer containing hydrogen on an oxide semiconductor layer using a gate insulating layer and a gate electrode layer as a mask is known. Yes. By increasing the hydrogen concentration in the oxide semiconductor layer, the resistance of the oxide semiconductor layer is reduced, source / drain regions are formed, and a coplanar structure TFT is obtained. In this structure, the parasitic resistance from the source / drain region to the channel region can be reduced, and the occurrence of current limitation can be suppressed.

  However, in the case of the TFT having the top gate type coplanar structure, it is necessary to form a gate insulating layer over the channel region of the oxide semiconductor layer. Therefore, when the gate insulating layer is formed by plasma chemical vapor deposition (CVD) or sputtering, damage to the interface between the gate insulating layer and the channel region of the oxide semiconductor layer is a problem. Become. In addition, the present inventors have clarified that this damage adversely affects the characteristics of the TFT, such as mobility, S value, and a decrease in stability against electrical stress.

  For this reason, it is desirable to form a bottom gate TFT in which damage to the interface between the gate insulating layer and the channel region of the oxide semiconductor layer is unlikely to occur. For this reason, in Patent Document 1, by using the channel protective layer as a mask, the resistance of the oxide semiconductor layer is reduced by hydrogen diffusion during the formation of the interlayer insulating layer, and the source / drain regions are formed, thereby forming the bottom gate type coplanar structure. An amorphous oxide semiconductor TFT is manufactured.

JP 2009-272427 A

  With the manufacturing method of Patent Document 1, a TFT having certain characteristics can be obtained. However, when the present inventors applied a positive gate bias stress to the oxide semiconductor TFT of Patent Document 1, the transfer characteristics do not shift in parallel to the positive direction, and the shape in the subthreshold region changes. The phenomenon that occurs was found. Specifically, the shift amount (ΔVon) of the rising voltage (Von) determined by the drain current value of the subthreshold region is compared to the shift amount (ΔVth) of the threshold voltage (Vth) determined by the drain current value of the on region. ) Was reduced. As described above, when an electric circuit is formed using TFTs having different ΔVth and ΔVon with respect to a positive gate bias stress, it is difficult to predict a change in TFT characteristics over time, and it is difficult to design an electric circuit.

  Therefore, an object of the present invention is to provide a bottom gate type thin film transistor in which a change in shape in a subthreshold region of transfer characteristics is reduced.

  In order to solve the above problems, according to the present invention, a gate electrode layer, a gate insulating layer, a channel region, a source region, and a drain region are formed of the same layer over a substrate, and the source region and the drain are formed. An oxide semiconductor layer having a region provided through the channel region is stacked in this order, and is close to the channel region at the end in the width direction in each of the source region and the drain region. The present invention provides a bottom-gate thin film transistor characterized in that at least a part of the region from the corner on the side is located inside the end of the channel region on the same side as the end.

  According to the present invention, it is possible to reduce a change in shape in the subthreshold region of the transfer characteristic when the transfer characteristic of the TFT with respect to positive gate bias stress is shifted in the positive direction. Thus, when the TFT of the present invention is used, the design of the electric circuit is facilitated, and the product design and manufacturing costs can be reduced.

It is a figure which shows typically an example of a structure of TFT of this invention. It is a figure which shows typically the cross-section of TFT of FIG. It is a figure which shows typically another example of a structure of TFT of this invention. It is a figure which shows typically the cross-section of TFT of FIG. It is a figure which shows the structure of the conventional TFT typically. It is a figure which shows the transfer characteristic of TFT of this invention. It is a figure which shows the transfer characteristic of the conventional TFT. It is a figure which shows the change of the transfer characteristic of TFT of this invention. It is a figure which shows the change of the transfer characteristic of the conventional TFT. It is a figure which shows the relationship between the shortest distance d and (DELTA) Vth- (DELTA) Von.

  Hereinafter, preferred embodiments of a bottom gate type thin film transistor (TFT) of the present invention will be described with reference to the accompanying drawings.

  FIG. 1 is a diagram showing a part of an oxide semiconductor TFT having a bottom gate type coplanar structure, which is an example of a preferred embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line A-A ′ of FIG. 1.

  1 and 2, 10 is a substrate, 11 is a gate electrode layer, 12 is a gate insulating layer, 13 is an oxide semiconductor layer, 13a is a channel region of the oxide semiconductor layer, 13b is a source region of the oxide semiconductor layer, 13c is a drain region of the oxide semiconductor layer. Reference numeral 14 denotes a channel protective layer, 15 denotes a protective layer, 16 denotes a contact hole, 17 denotes a source wiring layer, and 18 denotes a drain wiring layer. Reference numeral 19 denotes a patterning end of the channel region on the gate electrode layer, 20 denotes a boundary between the channel region and the source region, and 21 denotes a boundary between the channel region and the drain region.

  A flexible plastic substrate is preferably used as the substrate 10, and examples thereof include films of polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyimide, polycarbonate, and the like. Note that the surface of the substrate may be coated with a barrier coat layer formed of an insulating film, or a glass substrate, a stainless steel substrate coated with an insulating layer, or the like may be used.

  First, the gate electrode layer 11 is formed on the substrate 10 by sputtering, pulse laser vapor deposition (PLD method), electron beam vapor deposition, chemical vapor deposition (CVD), or the like. Thereafter, the gate electrode layer 11 is patterned by photolithography and etching. The gate electrode layer 11 may be any material as long as it has good electrical conductivity. For example, metal electrode materials such as metals such as Ti, Pt, Au, Ni, Al, and Mo, alloys thereof, and laminated films thereof, ITO An oxide conductor such as (Indium Tin Oxide) is preferably used.

  Next, gate insulation is performed by sputtering, pulse laser vapor deposition (PLD), electron beam vapor deposition, plasma CVD (PECVD) or the like so as to cover the gate electrode 11 on the substrate 10 having the gate electrode 11. Layer 12 is formed. The gate insulating layer 12 may be any material having good insulating characteristics. For example, it is preferable to use a silicon oxide film or a silicon nitride film.

  Subsequently, an oxide semiconductor layer 13 made of a metal oxide film is formed on the gate insulating layer 12 by sputtering, PLD, electron beam evaporation, or the like. Thereafter, the oxide semiconductor layer 13 is patterned by a photolithography method, an etching method, or the like. As the oxide semiconductor layer 13, an amorphous oxide semiconductor including at least one element selected from In, Ga, Zn, and Sn is preferably used.

  Next, a channel protective layer is formed on the oxide semiconductor layer 13 (on the channel region 13a of the oxide semiconductor layer) by sputtering, pulse laser deposition (PLD), electron beam deposition, plasma CVD (PECVD), or the like. 14 is formed. Thereafter, the channel protective layer 14 is patterned by a photolithography method and an etching method. The channel protective layer 14 that is in direct contact with the oxide semiconductor layer 13 is required to have a function that does not lower the resistance of the oxide semiconductor layer 13 (the channel region 13a of the oxide semiconductor layer) when a protective layer 15 described later is formed. Further, when an insulating layer containing hydrogen (protective layer 15) is formed over the channel protective layer 14, the amount of hydrogen permeation is controlled by the thickness of the channel protective layer 14, and the resistivity of the channel region 13a of the oxide semiconductor layer is later controlled. It is also necessary to have a function that can control this. Therefore, it is preferable to use an insulating layer containing oxygen such as a silicon oxide film or a silicon oxynitride film as the channel protective layer 14. There is no problem even if the composition of these insulating layers deviates from stoichiometry.

  The oxide semiconductor layer 13 on which the channel protective layer 14 is formed becomes a channel region 13a of the oxide semiconductor layer. A region of the oxide semiconductor layer 13 on which the channel protective layer 14 is not formed becomes a source region 13b of the oxide semiconductor layer and a drain region 13c of the oxide semiconductor layer by forming a protective layer 15 described later. . That is, the channel region 13a, the source region 13b, and the drain region 13c are formed of the same layer (oxide semiconductor layer 13), and the source region 13b and the drain region 13c are provided through the channel region 13a (FIG. 2). Further, in each of the source region 13b and the drain region 13c, at least a part of the end in the width direction from the corner on the side close to the channel region 13a is the end of the channel region 13a on the same side as the end. (Fig. 1). Further, the shape of the channel protective layer 14 is determined so that the channel region 13a, the source region 13b, and the drain region 13c have this configuration, and the channel protective layer 14 is patterned so as to have the shapes. The width direction is a direction perpendicular to the direction from the source region 13b to the drain region 13c.

  Here, an effect obtained by the above structure of the channel region 13a, the source region 13b, and the drain region 13c will be described.

In the conventional bottom gate type coplanar structure TFT, the difference between the shift amount of Vth (ΔVth) and the shift amount of Von (ΔVon) with respect to positive gate bias stress is large. This is considered to be caused by the difference in the state density change mechanism of the oxide semiconductor with respect to positive gate bias stress between the inside of the channel region and the end portion (patterning end) in the width direction of the channel region. Note that Vth in the present invention is calculated from an extrapolation point of an approximate straight line to √Id = 0 with respect to a plot of a value obtained by multiplying the gate voltage and drain current in the ON region of the transfer characteristic by a power of 1/2 (√Id). is there. Further, Von in the present invention is defined and calculated as a gate voltage when Id in the transfer characteristic is 10 ⁻¹⁰ A. At this time, the larger the value of ΔVth−ΔVon, the more the shape of the subthreshold region of the transfer characteristic changes.

  From this, if the change in the state density of the oxide semiconductor with respect to the stress at the patterning end of the channel region can be suppressed, the change in the state density of the stress oxide semiconductor occurs only inside the channel region, so the value of ΔVth−ΔVon is It will be smaller.

  Here, in the case of adopting the above configuration, as shown in FIG. 1, since there is a region where the source region and the drain region do not exist at the patterning end of the channel region, current can be reduced at the patterning end of the channel region. For this reason, it is possible to suppress the change in the state density of the oxide semiconductor with respect to the stress at the patterning end of the channel region and to reduce the value of ΔVth−ΔVon, that is, to reduce the shape change in the subthreshold region of the transfer characteristics. Conceivable.

  As described above, the effects of the present invention can be obtained by configuring the channel region 13a, the source region 13b, and the drain region 13c as described above. As long as the above configuration is satisfied, the pattern shape of the channel protective layer 14 is not limited. For example, as shown in FIG. 3, the channel protective layer 14 may be removed by etching only in regions desired to be the source region 13b and the drain region 13c. In this case, the cross-sectional view taken along the line AA ′ in FIG. As shown in FIG.

  In each of the source region 13b and the drain region 13c, at least a part of the end in the width direction from the corner near the channel region 13a and the end of the channel region 13a on the same side as the end The shortest distance is preferably 2.5 μm or more and 100 μm or less. This is because the effect of the present invention can be obtained with certainty if the shortest distance is 2.5 μm or more, as will be shown in the examples described later. In order to obtain the effect of the present invention more reliably, it is more preferable that the shortest distance is set to 5 μm or more as shown in Examples described later. The upper limit value of 100 μm for the shortest distance is a preferable value in consideration of reducing the occupied area because the occupied area of the TFT increases as the shortest distance increases.

  Subsequently, a protective layer 15 is formed over the oxide semiconductor layer 13 (on the region serving as the source region 13b and the region serving as the drain region 13c) and on the channel protective layer 14, and the source region 13b of the oxide semiconductor layer 13 is formed. The resistance of the drain region 13c is reduced. The protective layer 15 is required to have a function of reducing the resistance of the oxide semiconductor layer 13 when directly formed on the oxide semiconductor layer 13. The resistance of an oxide semiconductor can be reduced by adding hydrogen. Therefore, it is necessary to form an insulating layer containing hydrogen as the protective layer 15. Specifically, a silicon nitride film containing hydrogen, a silicon oxide film, a silicon oxynitride film, a silicon carbide film, and a laminated film thereof are preferable. There is no problem even if the composition of these insulating layers deviates from stoichiometry. As a formation method, a plasma CVD method using a source gas containing hydrogen is preferable because it has an effect of promoting diffusion of hydrogen into an oxide semiconductor by plasma. At this time, hydrogen in the raw material diffuses into the oxide semiconductor layer, and the resistance of the oxide semiconductor layer 13 in the region where the channel protective layer 14 is not formed is reduced. Thereby, the source region 13b and the drain region 13c are formed.

  Next, contact holes 16 are formed in the protective layer 15 by photolithography and etching. Subsequently, the source wiring layer 17 and the drain wiring layer 18 are formed by sputtering, pulse laser vapor deposition (PLD), electron beam vapor deposition, CVD, or the like in order to make electrical connection with the outside. The source wiring layer 17 and the drain wiring layer 18 may be any material having good electrical conductivity. For example, metal electrode materials such as metals such as Ti, Pt, Au, Ni, Al, and Mo, and alloys thereof, and the like. It is preferable to use an oxide conductor such as a laminated film or ITO. Thereafter, the source wiring layer 17 and the drain wiring layer 18 are patterned by photolithography and etching. Note that the source region 13b and the drain region 13c may be used for the source wiring layer 17 and the drain wiring layer 18 as they are.

  Thus, an oxide semiconductor TFT having a bottom gate type coplanar structure is completed.

  In the present invention, a plurality of the TFTs can be arranged two-dimensionally (arranged vertically and horizontally in a plane) on the substrate in this way.

  Examples of the present invention will be described in detail below, but the present invention is not limited to these examples.

(Example)
FIG. 1 (a cross-sectional view taken along the line AA ′ in FIG. 2) shows an oxide semiconductor TFT having a bottom gate type coplanar structure according to this embodiment.

  First, Mo having a film thickness of 100 nm was formed as a gate electrode layer 11 on the glass substrate 10 by a sputtering method. Thereafter, the gate electrode layer 11 was patterned by photolithography and etching.

Next, a 200 nm-thickness silicon oxide film was formed as a gate insulating layer 12 over the gate electrode layer 11 by a plasma CVD method. The substrate temperature during the formation of the silicon oxide film by the plasma CVD method was 340 ° C. SiH ₄ and N ₂ O were used as the process gas, and the gas flow ratio was SiH ₄ : N ₂ O = 1: 25. The input RF power density and pressure were 0.9 W / cm ² and 173 Pa, respectively.

Subsequently, an amorphous IGZO film having a thickness of 40 nm was formed as the oxide semiconductor layer 13 over the gate insulating layer 12 by a sputtering method. The oxide semiconductor layer 13 was formed at a substrate temperature of 120 ° C. using a DC sputtering apparatus. A polycrystalline sintered body having an InGaZnO ₄ composition was used as the target, and the input power was 300 W. The atmosphere during film formation was set to a total pressure of 0.5 Pa, and the gas flow rate ratio at that time was Ar: O ₂ = 87: 13. Thereafter, the oxide semiconductor layer 13 was patterned by a photolithography method and an etching method.

Next, a 300-nm-thick silicon oxide film was formed as the channel protective layer 14 over the oxide semiconductor layer 13 (on the channel region 13a of the oxide semiconductor layer) by a plasma CVD method. The substrate temperature during the formation of the silicon oxide film by the plasma CVD method was 250 ° C. SiH ₄ and N ₂ O were used as the process gas, and the gas flow ratio was SiH ₄ : N ₂ O = 1: 25. The input RF power density and pressure were 0.9 W / cm ² and 173 Pa, respectively. Then, patterning by a photolithography method and an etching method was performed, and the channel protective layer 14 was formed with the pattern of FIG. At this time, in each of the source region and the drain region, at least a part of the end in the width direction from the corner on the side close to the channel region, and the end of the channel region on the same side as the end TFTs having the shortest distance d of 2.5 μm, 5 μm, and 10 μm were produced.

Subsequently, a 300 nm-thick silicon oxynitride film is formed as a protective layer 15 on the oxide semiconductor layer 13 (on the region to be the source region 13b and the region to be the drain region 13c) and on the channel protective layer 14 by plasma CVD. Formed by. The substrate temperature during the formation of the silicon oxynitride film by the plasma CVD method was 250 ° C. SiH ₄ , N ₂ O, and N ₂ were used as process gases, and the gas flow rate ratio was SiH ₄ : N ₂ O: N ₂ = 4: 5: 95. The input RF power density and pressure were 0.9 W / cm ² and 150 Pa, respectively.

  Next, after forming the contact hole 16 in the protective layer 15 by the photolithography method and the etching method, Mo having a thickness of 100 nm was formed as the source wiring layer 17 and the drain wiring layer 18 by the sputtering method. Thereafter, the source wiring layer 17 and the drain wiring layer 18 were patterned by a photolithography method and an etching method.

  Finally, annealing at 270 ° C. for 1 hour in the atmosphere was performed in a heating furnace to remove damage caused by dry etching or the like.

  Through the above process, the oxide semiconductor TFT of this example was completed.

  The following evaluation was performed on 13 oxide semiconductor TFTs in a plane of a 4-inch substrate manufactured in this example.

  First, the transfer characteristics of the TFT manufactured in this example were measured. The result is shown in FIG. As is apparent from FIG. 6, the transfer characteristics were good regardless of the length of the shortest distance d.

  Next, a stress test was performed on the TFT manufactured in this example (the shortest distance d = 5 μm), and the transfer characteristics before and after the stress test were measured. The stress conditions were a temperature of 60 ° C., a gate bias of +20 V, and a stress time of 10,000 seconds. The result is shown in FIG. FIG. 8A shows a case where a logarithmic plot is used, and FIG. 8B shows a case where a linear plot is used. As can be seen from FIG. 8, the transfer characteristics are shifted in the positive direction in both the ON region and the sub-threshold region, and almost no change in the shape of the sub-threshold region in the transfer characteristics was observed.

  FIG. 10 shows the dependence of ΔVth−ΔVon on the shortest distance d in the stress test. From FIG. 10, ΔVth−ΔVon is small in the TFT manufactured in this example (the shortest distance d = 2.5 μm to 10 μm). Therefore, it is apparent that the structure of the present invention has the effect of reducing ΔVth−ΔVon, that is, the effect of reducing the shape change in the subthreshold region of the transfer characteristics. Further, when the shortest distance d is 5 μm or more, the dependence of ΔVth−ΔVon on the shortest distance d is saturated, and when the shortest distance d is preferably 2.5 μm or more, the effect of the present invention can be obtained. It can be seen that the effect of the present invention can be obtained when the thickness is preferably 5 μm or more.

(Comparative example)
As a conventional oxide semiconductor TFT, an oxide semiconductor TFT having a bottom gate type coplanar structure shown in FIG. 5 was manufactured. It was fabricated in the same manner as in Example 1 except that the shortest distance d = 0.

  Evaluation similar to Example 1 was performed with respect to 13 oxide semiconductor TFTs in the plane of the 4-inch substrate manufactured in this comparative example.

  First, the transfer characteristics of the TFT manufactured in this comparative example were measured under the same conditions and method as in Example 1. The result is shown in FIG. As shown in FIG. 7, the transfer characteristics were good as in Example 1.

  Next, a stress test of the TFT manufactured in this comparative example was performed under the same conditions and method as in Example 1. The result is shown in FIG. FIG. 9A shows a case where a logarithmic plot is used, and FIG. 9B shows a case where a linear plot is used. As shown in FIG. 9, the transfer characteristic shifts in the negative direction in the subthreshold region, while the transfer characteristic shifts in the positive direction in the on region. From this, it is clear that the shape of the subthreshold region in the transfer characteristic has changed.

  Further, from FIG. 10, ΔVth−ΔVon is large in the TFT manufactured in this comparative example (the shortest distance d = 0). Therefore, it can be seen that the structure of this comparative example cannot obtain the effect of reducing ΔVth−ΔVon.

  10: substrate, 11: gate electrode layer, 12: gate insulating layer, 13: oxide semiconductor layer, 13a: channel region of oxide semiconductor layer, 13b: source region of oxide semiconductor, 13c: drain region of oxide semiconductor , 14: channel protective layer, 15: protective layer, 16: contact hole, 17: source wiring layer, 18: drain wiring layer

Claims (5)

On the board,
A gate electrode layer;
A gate insulating layer;
An oxide semiconductor layer in which a channel region, a source region, and a drain region are formed of the same layer, and the source region and the drain region are provided through the channel region;
Are stacked in this order,
In each of the source region and the drain region, at least a part of the end in the width direction from the corner on the side close to the channel region is more than the end of the channel region on the same side as the end. A bottom-gate thin film transistor, which is located inside.   In each of the source region and the drain region, the shortest distance between the region at the end in the width direction and the end of the channel region on the same side as the end is 2.5 μm or more and 100 μm or less. The bottom-gate thin film transistor according to claim 1.   3. The bottom-gate thin film transistor according to claim 1, wherein the oxide semiconductor layer is made of an amorphous oxide semiconductor containing at least one element of In, Ga, Zn, and Sn.   4. The bottom-gate thin film transistor according to claim 1, wherein a channel protective layer made of an insulating layer containing oxygen is formed on the channel region. 5.   5. The bottom-gate thin film transistor according to claim 4, wherein an insulating layer containing hydrogen is formed on the source region and the drain region.

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