JP2010165961A - Thin-film transistor, display device, and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a TFT with a small parasitic capacitance wherein the width of a gate electrode is made nearly as minimum as a processing size, in the TFT of bottom gate self-alignment type. <P>SOLUTION: The self-alignment type TFT is formed by the backside irradiation of the ultraviolet rays using the gate electrode as a mask, to a semiconductor layer consisting of an amorphous oxide containing In, Ga and Zn. The semiconductor layer is irradiated by ultraviolet rays so that high electric conduction is achieved to an extent where it functions as a source electrode from the gate electrode to a little interior due to the impact of the diffraction of ultraviolet rays, and it functions also as a drain electrode, as a result, the channel length serving as length somewhat shorter than the width of the gate electrode. Thereby, it is made possible to shorten the width of the gate electrode to nearly as minimum as a processing size. Accordingly, the TFT parasitic capacitance can also be reduced. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a thin film transistor, a display device, and a manufacturing method thereof, and more particularly to a thin film transistor, a display device, and a manufacturing method thereof using a metal oxide amorphous semiconductor thin film.

  Currently, thin film transistors (hereinafter referred to as TFTs) using an amorphous silicon thin film are used as switching elements for liquid crystal display devices and the like and are put into practical use in monitors for television receivers and personal computers. On the other hand, in recent years, semiconductor elements using metal oxide semiconductor thin films have attracted attention. This thin film can be formed at a low temperature and has a feature that a film transparent to visible light can be formed. It is flexible and transparent on a transparent substrate such as a plastic substrate or a film. A TFT can be formed (Patent Document 1).

A semi-insulating transparent amorphous thin film made of an oxide containing In, Ga and Zn is known as an oxide semiconductor film used for an active layer of a TFT. and the structure of the top gate type TFT using a material obtained by laminating an Au film to a layer of conductivity of large InGaZnO _{3 (ZnO) 4} as the source and drain electrodes is disclosed, additionally, amorphous InGaZnO ₄ TFT is amorphous silicon thin film transistor It has been disclosed that the mobility is much higher than that of Patent Document 2 (Patent Document 2). Currently, active research and development is being conducted so that TFTs having such excellent characteristics can be used not only for liquid crystal display devices but also for other display devices.

JP 2000-150900 A JP 2006-165529 A

  Conventionally, when forming a bottom gate type TFT using amorphous silicon, a back channel type TFT has a large gate-source parasitic capacitance Cgs, a gate-drain parasitic capacitance Cgd, and a self-aligned channel. Even in the protection type TFT, the channel length L is required to be about three times the minimum processing dimension F, and it is difficult to reduce the gate-source parasitic capacitance Cgs and the gate-drain parasitic capacitance Cgd.

  FIG. 4 shows a conventional example of a TFT, and is a schematic cross-sectional structural view of a self-aligned and channel protective TFT having amorphous silicon as a semiconductor layer of the TFT. FIG. 4A is a plan configuration diagram, and FIG. 4B is a schematic cross-sectional configuration diagram in the direction of the arrow in the B-B ′ line in FIG. In FIG. 4A, the gate insulating film 13 and the passivation layer 19 are removed for easy understanding. Note that the n + amorphous silicon layers 24 s and 24 d and the amorphous silicon semiconductor layer 14 p are formed in such a manner that their side ends coincide with part of the side ends of the source electrode 25 and the drain electrode 26, so that they can be seen in a plan view. This is not possible and is not shown in the plan view of FIG. In each drawing used for description in this specification, the scale or aspect ratio is appropriately changed for convenience.

  The TFT 20p extends over the gate electrode 12 through the gate insulating film 13 formed on the gate electrode 12 made of a light-shielding metal, the gate insulating film 13 formed thereon and having insulating properties. And the amorphous silicon semiconductor layer 14p formed on the substrate. An insulating channel protective film 18p (also called an etching protective film) is formed on the amorphous silicon semiconductor layer 14p, and n + is a low-resistance semiconductor layer having a higher conductivity than the amorphous silicon semiconductor layer 14p. Amorphous silicon layers 24s and 24d are formed. A source electrode 25 and a drain electrode 26 made of metal are formed on the n + amorphous silicon layers 24 s and 24 d, respectively, and an insulating passivation layer 19 is formed on the source electrode 25 and the drain electrode 26. ing. A source region 15p and a drain region 16p are formed with a channel region 17p that is a part of the amorphous silicon semiconductor layer 14p interposed therebetween. The source region 15p and the drain region 16p are both part of the amorphous silicon semiconductor layer 14p.

  As a manufacturing method of such a TFT 20p, first, after sequentially forming a gate electrode 12 and a gate insulating film 13 on a substrate 11, a semiconductor layer 14p made of amorphous silicon is formed by a CVD method. Next, a channel protective film 18p made of a silicon oxide material is formed, and a layer 24 made of n + amorphous silicon containing P (phosphorus) is further formed by a CVD method. Thereafter, a metal layer to be the source electrode 25 and the drain electrode 26 is formed by sputtering or the like. Then, after applying a resist in a predetermined shape on the metal layer, the metal layer is etched to form the source electrode 25 and the drain electrode 26. Further, the n + amorphous silicon layers 24s and 24d and the amorphous silicon semiconductor layer 14p are patterned by the same PEP (Photo Engraving Process) by further etching using the same resist. The channel region 17p is protected from being etched by the channel protective film 18p. Thereafter, a passivation layer 19 is formed to form the TFT 20p shown in FIG.

  The channel protective film 18p is formed by depositing a silicon oxide-based material, and then applying a resist thereon, and using the gate electrode 12 as a shadow mask, from the back surface, that is, from the direction of the substrate 11 toward the channel protective film 18p. It is formed by performing exposure (backside exposure) and further undergoing predetermined surface exposure and etching. As a result, the channel protective film 18p is formed in a self-aligned manner with respect to the gate electrode 12 (self-alignment). Accordingly, the shift in the channel length direction of the channel protective film 18p with respect to the gate electrode 12 is extremely small, and the variation (in-plane variation) within the substrate is extremely small.

  Since the resist is exposed to the inner side of the gate electrode 12 by the distance of Ls2 and Ld2 due to the influence of diffraction or the like during the backside exposure, the side edge of the channel protective film 18p is more than the side edge of the gate electrode 12, respectively. Molded inward by the dimensions of Ls2 and Ld2. In other words, these dimensions are smaller than the dimension Lg of the gate electrode 12 in the channel length direction. In general, the dimensions of Ls2 and Ld2 are, for example, constant dimensions of 0.5 to 1.0 μm. Thus, even in the channel protective film 18p formed with a slightly shortened dimension in the channel length direction, the channel protective film 18p is displaced at any position on the substrate with respect to the gate electrode 12 in the channel length direction. The TFT is constant and the in-plane variation is extremely small. In the TFT 20p formed in this way, a region where the channel protective film 18p and the gate electrode 12 overlap in the plan view in the semiconductor layer 14p becomes the channel region 17p, and thus the dimension of the channel protective film 18p in the channel length direction. Becomes the channel length L of the TFT 20p.

  A region 15c that is a part of the source region 15p and covers Ls2 faces the gate electrode 12 with the gate insulating film 13 interposed therebetween, and the gate electrode 12 and the region 15c overlap in plan view. Therefore, in this region 15c, a parasitic capacitance Cgs1 generated by the overlap between the gate electrode 12 and the region 15c in the gate-source parasitic capacitance Cgs is generated. Similarly, in the region 16c which is a part of the drain region 16p and is applied to Ld2, a parasitic capacitance Cgd1 generated by the overlap between the gate electrode 12 and the region 16c in the gate-drain parasitic capacitance Cgd is generated. These parasitic capacitances will be described later.

  It is necessary to form the source electrode 25 and the drain electrode 26 apart from each other by a distance of the minimum processing dimension F, similarly to the n + amorphous silicon layers 24s and 24d formed in these lower layers. Furthermore, when forming the source electrode 25 and the drain electrode 26, it is necessary to consider the size of the mask misalignment of the source electrode 25 and the drain electrode 26 with respect to the channel protective film 18p. The minimum processing dimension F is determined by exposure accuracy, etching processing accuracy, and the like. For example, in the field of liquid crystal display devices, F is 4 to 5 μm. If F is 4 μm and the maximum alignment displacement of the mask is 3.5 μm, the source electrode 25 (and the n + amorphous silicon layer 24s connected to the lower layer) is at least in the direction from the side edge of the channel protective film 18p to the inside thereof. It is necessary to design the pattern in advance so as to extend Ls1 = 3.5 μm or more. Similarly, for the drain electrode 26, Ld1 needs to be 3.5 μm or more. Then, if Ls2 = Ld2 = 0.5 μm, the dimension Lg of the gate electrode 12 in the channel length direction is at least as large as Ld2 + Ld1 + F + Ls1 + Ls2 = 12 μm. The channel length L is 11 μm, and this dimension is about three times the minimum processing dimension F as described above. Such a TFT having a long channel length not only hinders integration but also increases the gate-source parasitic capacitance Cgs and the gate-drain parasitic capacitance Cgd. As will be described later, for example, in the case of a liquid crystal display device in which a liquid crystal as a load is connected to a source electrode, an increase in Cgs becomes a problem.

  The relationship between the channel length L, the gate-source parasitic capacitance Cgs, and the gate-drain parasitic capacitance Cgd is as follows. When the TFT 20p transitions from the on state (selection period) to the off state (non-selection period), the potential or the charging time of the source region 15p and the drain region 16p is not only the Cgs1 and Cgd1, but the channel that was in the on state. Although the region 17p (region overlapping the channel protective film 18p in plan view) and the gate electrode 12 are also affected by parasitic capacitance in the plan view, this parasitic capacitance is almost on the source side and drain side of the channel region 17p. Divided into two. The parasitic capacitance Cgs2 corresponding to almost half of the area of the channel region 17p contributes to the source-side parasitic capacitance Cgs, and the parasitic capacitance corresponding to the other half contributes to the drain-side parasitic capacitance Cgd. Therefore, the gate-source parasitic capacitance Cgs depends on the sum of the area of the region where the gate electrode 12 and the source region 15p overlap in plan view (for Cgs1) and the half area of the channel region 17p (for Cgs2). And is affected by Cgs1 and Cgs2. Therefore, when the channel length L is long, Cgs2 increases, so that the gate-source parasitic capacitance Cgs also increases. The same applies to Cgd on the drain side.

  As described above, in the TFT having the structure as in the conventional example, with respect to Cgs1, the amount generated by the wraparound due to diffraction or the like at the time of exposure (the portion of the region 15c relating to Ls2) only contributes to Cgs1. Cgs1 can be made very small, and Cgs1 has little influence even if the mask for forming the source electrode and the drain electrode is displaced in the channel length direction. However, since the TFT having such a conventional structure has a channel length L that is about three times as long as the minimum processing dimension F, Cgs2 is large and eventually Cgs is large. In order to reduce Cgs2, the channel width W may be reduced, but the driving capability is also reduced, and there remains a problem. As a result, in the conventional bottom gate type self-aligned TFT, the channel length L is required to be about three times the minimum processing dimension F. Therefore, the gate-source parasitic capacitance Cgs and the gate-drain parasitic capacitance Cgd are reduced. It was difficult.

  In summary, in the case of the conventional bottom gate type self-aligned TFT, the channel protective film 18p on the channel region 17p is formed to be slightly smaller than the dimension Lg of the gate electrode 12 in the channel length direction by backside exposure, thereby protecting the channel. The semiconductor layer 14p and the source electrode 25 or the drain electrode 26 were electrically connected at the side end of the film 18p. That is, the channel length L is defined by the width of the channel protective film 18p. On the other hand, the distance between the source electrode 25 and the drain electrode 26 is defined by the minimum processing dimension F, and further, the source electrode 25, the drain electrode 26, and the channel protective film 18p need to overlap each other with a width in consideration of misalignment. It was. As a result, the dimension Lg of the gate electrode 12 in the channel length direction is required to be about three times the minimum processing dimension F, and it is difficult to reduce the gate-source parasitic capacitance Cgs and the gate-drain parasitic capacitance Cgd. It was.

  As another structure of the bottom gate type TFT, a so-called back channel type TFT not using a channel protective film has been proposed in addition to the channel protective type TFT described above. In the back channel TFT, the minimum processing dimension F can be formed as the channel length L. However, due to the structure of the back channel TFT, the gate-source parasitic capacitance Cgs1 due to the overlap between the gate electrode and the source electrode or the source region and its variation tend to be large.

  Thus, when Cgs and Cgd are large and vary over the entire substrate, when such a TFT is used in a liquid crystal display device as a switching element of a liquid crystal pixel, for example, variation in luminance and luminance unevenness on the display screen are remarkable. The problem that it becomes becomes. If the side where the pixel electrode that applies an electric field to the liquid crystal is connected is called the source, the presence of Cgs causes the pixel potential to drop by the so-called penetration voltage (feedthrough voltage) during the transition, thereby improving the display quality of the liquid crystal. In addition to the deterioration, the Cgs varies, and the punch-through voltage also varies, and the variation in luminance and the luminance unevenness on the display screen become more remarkable. Further, the punch-through voltage caused by Cgs further varies depending on the length of the wiring from the feeding end of the scanning line to the gate electrode of the TFT in each pixel, in other words, the position of the pixel in the row direction. That is, the waveform of the scanning signal is rounded due to the distributed resistance or the distributed capacitance of the scanning line, and the degree of the rounding increases as the distance from the power supply end increases. As a result, the penetration voltage is moved away from the power supply end by the so-called recharging effect. This causes a so-called luminance gradient phenomenon in which the luminance of a pixel changes as it moves away from the power supply end as compared with a pixel close to the power supply end of the scanning signal on the display screen (see Japanese Patent Application Laid-Open No. 2004-258498). . In addition to these, when the mask misalignment is a misalignment rotated in the θ direction, the variation in the punch-through voltage becomes complicated, and particularly in the case of a large-screen display device, the entire screen. It is an important issue to improve display quality by suppressing variations in luminance and the like and luminance unevenness.

In the case of a liquid crystal display device, as a method of reducing the in-plane distribution of the punch-through voltage due to mask misalignment or the like, a structure having a storage capacitor Cs having a size equal to or larger than that of the conventional one may be used. Are known. If the C _LC and the liquid crystal capacitance per pixel, punch-through voltage is, Cgs / proportional to _{(Cgs + C LC + Cs)} , the voltage itself penetration by those of larger capacity Cs compared Thus the Cgs And the variation in punch-through voltage due to the variation in Cgs can be reduced. However, when a light-shielding metal is used for one electrode constituting Cs, the light-shielding area due to Cs increases, and this method causes another problem that the aperture ratio of the pixel portion cannot be improved.

  When a transparent amorphous oxide semiconductor composed of an oxide containing In, Ga and Zn, for example, is used as a semiconductor layer of a TFT, whether it is a channel protection type or a back channel type, this is the case. In general, since the mobility of such semiconductors is high, it is possible to reduce the size of the TFT. However, as long as the minimum processing size F determined by the exposure accuracy and etching processing accuracy does not change, the smaller the TFT size, the more the mask alignment shift. The effect of is relatively large. Therefore, in order to use a TFT using a semiconductor with high mobility for a display device or the like and take advantage of its high mobility, the channel length L of the TFT is shortened and a self-aligned TFT is formed to make a parasitic. It is more important to reduce the capacitances Cgs and Cgd.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a TFT structure having a small parasitic capacitance and variation thereof, and a manufacturing method thereof. Another object of the present invention is to provide a display device with high display quality using such TFT and a method for manufacturing the same.

  The thin film transistor manufacturing method of the present invention includes a first step of forming a light-shielding gate electrode on a substrate, a second step of forming a gate insulating film on the gate electrode, and an In on the gate insulating film. , A third step of forming a semiconductor layer made of an amorphous oxide containing Ga and Zn, and by irradiating the semiconductor layer with ultraviolet light using the gate electrode as a shadow mask, the semiconductor layer is more conductive than the semiconductor layer before irradiation. And a fourth step of forming an amorphous source region or drain region having a high rate.

  As described above, according to the present invention, the amorphous oxide containing In, Ga, and Zn is used as the material of the semiconductor layer of the thin film transistor. Therefore, the conductivity of the semiconductor layer can be increased by irradiating it with ultraviolet rays. . Then, by selectively irradiating a part of the semiconductor layer with such ultraviolet rays, the conductivity can be increased only in the irradiated region. Therefore, by selectively irradiating ultraviolet rays to regions to be the source region and the drain region in the semiconductor layer, a source region and a drain region having a conductivity that can be used as an electrode can be formed. Therefore, it is not necessary to separately form a low-resistance semiconductor layer such as an n + amorphous silicon layer as in the conventional example in order to connect to a source electrode and a drain electrode made of metal. On the other hand, the conductivity of the region of the semiconductor layer that has not been irradiated with ultraviolet rays is maintained as it was before the irradiation, so that the region that should become the channel region of the thin film transistor should not be irradiated with ultraviolet rays. Thus, the region becomes a region having conductivity that can be used as a channel of the thin film transistor.

  Moreover, according to the present invention, the three regions of the source region, the drain region, and the channel region are formed in a self-aligned manner with respect to the gate electrode by irradiating the back surface with ultraviolet rays using the gate electrode as a shadow mask. (Self-alignment) The channel length L of the thin film transistor formed in such a self-alignment is the same as the dimension Lg in the channel length direction of the gate electrode 12 or slightly shorter than the dimension Lg due to the influence of ultraviolet diffraction or the like. In the thin film transistor thus formed, the overlap between the gate electrode and the source region or the drain region in plan view is very small. Therefore, the gate-source parasitic capacitance Cgs1 and the gate-drain parasitic capacitance Cgd1 generated by the overlap are as follows. Since it is extremely small and formed in a self-aligned manner, the variation in Cgs1 and Cgd1 is extremely small.

  As described above, the highly conductive source and drain regions are formed in a self-aligned manner, and the source and drain regions and the channel region are always electrically connected. The distance between the source electrode and the drain electrode and the distance between the n + amorphous silicon layers are not less than the minimum processing dimension F, and the source electrode, the drain electrode, and the n + amorphous silicon layer are always at the end of the channel region even when there is a mask misalignment. The restriction that the pattern must be designed so as to connect to the part is solved. Therefore, in the present invention, the dimension Lg of the gate electrode in the channel length direction is about the minimum processing dimension F, and does not need to be increased to about three times the minimum processing dimension F as in the prior art. Therefore, the channel length L of the TFT of the present invention is also the same as Lg or shorter than Lg by Ls2 and Ld2, and the channel length L is approximately 1/3 of the conventional size, that is, substantially the same as the minimum processing dimension F or The dimension is shorter than F by Ls2 and Ld2. As a result, Cgs2 determined by the channel length L of Cgs is reduced to about ３ compared to the conventional case. Further, since the source electrode and the drain electrode are not affected by the mask misalignment with respect to the gate electrode as in the conventional example, the in-plane variation of Cgs2 itself is reduced. Thus, since the magnitude | size and dispersion | variation of Cgs1 and Cgs2 become small, the magnitude | size and variation of the gate-source parasitic capacitance Cgs become also extremely small. The same applies to the parasitic capacitance Cgd between the gate and the drain.

  The thin film transistor manufacturing method of the present invention is characterized in that a dimension of the gate electrode in a channel length direction is a minimum processing dimension. By adopting such a configuration, the channel length can be shortened, so that Cgs2 and Cgd2 determined by the dimension of the channel length can be reduced. The thin film transistor manufacturing method of the present invention is characterized in that a resistance of the source region or the drain region after irradiation with the ultraviolet light is lower than an on-resistance of the thin film transistor. By adopting such a configuration, a decrease in signal level such as an image signal due to the resistance of the entire source region or the entire drain region can be reduced.

  The thin film transistor manufacturing method of the present invention is characterized in that the impurity concentration of the channel region of the semiconductor layer is the same as the impurity concentration of the source region or the drain region. Because of this configuration, it is not necessary to perform a process such as ion doping when forming a source region or a drain region having a higher conductivity than the channel region as in the conventional case, which not only contributes to the rationalization of manufacturing equipment. Since damage due to this can be avoided, the reliability of the thin film transistor is improved. The thin film transistor manufacturing method of the present invention is characterized in that the light source for irradiating ultraviolet rays is a surface light source. Since this invention takes such a structure, it can irradiate an ultraviolet-ray uniformly at once to the wide irradiation area which covers the whole board | substrate. Further, since a surface light source is used, it is not necessary to scan the substrate as in the case of a laser light source with a narrow beam spot, and double irradiation of the semiconductor layer by scanning does not occur. Therefore, it is possible to irradiate ultraviolet rays with uniform irradiation energy, and as a result, in the case of forming a large number of thin film transistors over the entire display screen of a large area, not only simplification of the process and improvement of mass productivity but also the thin film transistor A variation in characteristics can be suppressed and uniform, and a display device with high display quality and free from variations in luminance and luminance can be obtained.

  The thin film transistor manufacturing method of the present invention is characterized in that the light source for irradiating ultraviolet rays is a mercury lamp. Since the present invention adopts such a configuration, a lamp that irradiates ultraviolet rays having a specific range of wavelengths can be used instead of a laser light source. Therefore, it is possible to avoid problems due to heat generation of the substrate by the laser light, and it is possible to use a plastic film substrate. Further, an ultraviolet irradiation device that is less expensive than a laser beam irradiation device can be used.

The thin film transistor manufacturing method of the present invention is characterized in that the wavelength of the ultraviolet ray ranges from 270 nm to 450 nm. By irradiating ultraviolet rays in such a wavelength range, the conductivity can be improved to an appropriate level using the irradiated semiconductor region as a source electrode and a drain electrode. In the method of manufacturing a thin film transistor of the present invention, the cumulative irradiation energy density of ultraviolet rays in the fourth step is (309 · n) to (309) when the conductivity is increased 10 ⁿ times (where 0 <n ≦ 6). 392 · n) J / cm ² . Since the present invention has such a configuration, if the target conductivity is set, the cumulative irradiation energy density of ultraviolet rays, the irradiation time, and the like can be calculated in advance.

The thin film transistor manufacturing method of the present invention is characterized in that an integrated irradiation energy density of ultraviolet rays in the fourth step is 1332 J / cm ² or more. Since the present invention has such a structure, a semiconductor layer having sufficient conductivity to function as a source region or a drain region can be formed. Manufacturing method of a thin film transistor of the present invention, the irradiation energy density of the ultraviolet in the fourth step, characterized in that it is a 100mJ / sec · cm ^2. By adopting such a configuration, the present invention can perform irradiation using a general ultraviolet irradiation apparatus used for other purposes as long as the irradiation energy density is obtained. Therefore, rationalization of manufacturing equipment can be achieved.

  The display device manufacturing method of the present invention includes a step of forming a thin film transistor by using the above-described method of manufacturing a thin film transistor, and a step of disposing an electro-optic member that controls modulation of light by the thin film transistor and serves for display. Features. By adopting such a configuration, the thin film transistor according to the present invention can be used as an active element for controlling light modulation in a display device in which display is performed by an electro-optic member having a light modulation function. Can be manufactured. As such an electro-optical member, for example, a liquid crystal, an OLED (Organic Light Emitting Diode), a microcapsule for electrophoresis, or the like can be considered. In such an electro-optical member, light is modulated by the value of voltage or current applied to the electro-optical member. For example, in the case of a liquid crystal, the transmitted light can be modulated by a combination with an optical member such as a polarizing plate, and in the case of an OLED that emits light by itself, the light emission can be modulated. In any case, such light modulation can be used for pixel gradation control. Therefore, the gradation can be controlled by controlling the voltage or current to be applied by the TFT according to the present invention. By using such an electro-optical member as a member for display, the influence of parasitic capacitance is reduced. Various display devices with high display quality, such as liquid crystal display devices, OLED display devices, EPID (ElectroPhoretic Image Display) such as electronic paper, and the like can be manufactured.

  The display device manufacturing method of the present invention is characterized in that the electro-optical member is a liquid crystal. By adopting such a configuration, in the display device using liquid crystal as the electro-optical member, the effect of improving the display quality becomes more apparent. That is, since the punch-through voltage due to Cgs is reduced and equalized, luminance variation and luminance unevenness on the display screen are remarkably reduced, and display quality can be improved. In addition, the recharging effect is reduced, the luminance gradient phenomenon is also reduced, and the display quality is improved. In addition, since the Cgs value itself is reduced and the variation thereof is reduced, the storage capacitor Cs can also be reduced from the viewpoint of measures against Cgs. Accordingly, the area of the electrode made of a light-shielding metal constituting the storage capacitor Cs can be reduced, so that the aperture ratio of the pixel portion is improved. Therefore, it is possible to provide a method for manufacturing a large-screen display device with little luminance unevenness and luminance gradient and high display quality.

  The thin film transistor of the present invention includes a gate electrode having a light-shielding property formed on a substrate, a gate insulating film formed on the gate electrode, a channel region, and ultraviolet rays on the semiconductor layer using the gate electrode as a shadow mask. A semiconductor composed of an amorphous oxide containing In, Ga, and Zn formed on the gate insulating film, including an amorphous source region or drain region whose conductivity is higher than that before irradiation by irradiation And a layer. The display device of the present invention includes the thin film transistor, and an electro-optical member that controls light modulation by the thin film transistor and provides display.

  Since the present invention has such a configuration, it can provide a structure of a self-aligned bottom-gate TFT with a small parasitic capacitance and its variation and a manufacturing method thereof. In addition, the present invention can provide a display device with high display quality using such a TFT and a manufacturing method thereof.

It is explanatory drawing of the manufacturing process of TFT which is one Embodiment of this invention. It is a graph which shows the relationship between the electrical conductivity of the amorphous IGZO semiconductor layer of this invention, and ultraviolet irradiation time. 1 is a schematic configuration diagram of a liquid crystal display device according to an embodiment of the present invention. It is a schematic block diagram of the conventional TFT.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. For convenience, in this specification, of the TFT source and drain, the side to which the load is connected is called the source and the other is called the drain. However, in the present invention, the source is called the drain and the drain is called the drain. Even if it is called a source, its action and effect are the same.

[TFT]
The configuration of the bottom gate type TFT will be described with reference to FIG. FIG. 1C is a schematic cross-sectional configuration diagram showing the TFT 20 when the formation of the passivation layer 19 is completed. The TFT 20 is formed on the gate electrode 12 formed on the substrate 11, the gate insulating film 13 which is the first insulating layer formed on the gate electrode, and the gate insulating film 13. The semiconductor layer 14 includes a region 16 and a channel region 17 and includes an oxide semiconductor. Note that the semiconductor layer 14 is formed at a position over the gate electrode 12 with the gate insulating film 13 interposed therebetween, and the channel region 17 that is a part of the semiconductor layer 14 has a gate electrode 12 as described later. Is formed at a position sandwiched between the source region 15 and the drain region 16 in a self-aligning manner. Then, a channel protective film 18 as a second insulating layer is formed on the semiconductor layer 14, and on the source region 15 and the drain region 16 through contact holes 23 s and 23 d penetrating the channel protective film 18, respectively. A source electrode 25 and a drain electrode 26 that are electrically connected to the source region 15 and the drain region 16 are formed. These are covered with a passivation layer 19 which is a third insulating layer.

  Each member of the TFT 20 will be described in more detail. As the substrate 11, a plastic substrate can be used in addition to a glass substrate or a quartz substrate which is a substrate having insulation and transparency. In order to faithfully reproduce the display color of the display device, the substrate is more preferably transparent to visible light.

  The gate electrode 12 is formed by patterning the first metal layer. The first metal layer may be, for example, a single layer film of AlNd, Al, or Mo, or a laminated film formed by combining arbitrary elements selected from AlNd, Al, Mo, and Cu. For example, a wiring such as a scanning line or a signal line of an active matrix display device is also formed from a first metal layer. Such a wiring contains Al, and an oxide semiconductor or ITO (indium tin) is used. When there is a possibility of connecting to a transparent conductive layer such as an oxide (Indium Tin Oxide), it is desirable that the first metal layer has a laminated structure. For example, an upper layer that may be connected to ITO or the like in a later process is preferably a metal containing Mo, and a lower layer is a metal layer containing Al, such as AlNd. By adopting such a material and structure, it is possible to avoid electrical corrosion at the interface between ITO and Al and to achieve good electrical connection. The thickness of the first metal layer is desirably 200 nm to 400 nm, and more desirably 300 nm. When it is necessary to prevent the TFT characteristics from being affected by external light, it is desirable to use a material with high light shielding properties for the first metal layer.

  As the material of the gate insulating film 13 which is the first insulating layer, a silicon oxide-based or silicon nitride-based SiNx, SiOx or SiOxNy single layer film, or a laminated film in which these are combined can be used. Alternatively, liquid silicon oxide can be used. Thereby, an insulating and transparent layer can be formed. The gate insulating film 13 is generally formed so as to cover the entire substrate 11. As a result, the gate electrode 12 is covered with the gate insulating film 13. The thickness of the gate insulating film 13 is desirably 100 nm to 500 nm, and more desirably 250 nm to 300 nm.

  The material of the semiconductor layer 14 is desirably a transparent amorphous semiconductor made of an oxide containing In, Ga, and Zn (hereinafter referred to as IGZO). The semiconductor layer 14 is formed as a single island-shaped molded product without the three regions of the source region 15, the drain region 16, and the channel region 17 being separated from each other. When the semiconductor layer 14 is formed, the conductivity is the same in any of these three regions, but as described later, by selectively irradiating ultraviolet rays in a predetermined step after the formation of the semiconductor layer, The drain region 16 and the source region 15 are formed to have higher conductivity than the channel region 17. Details of the relationship between ultraviolet irradiation and conductivity will be described later. The thickness of the semiconductor layer 14 is not particularly limited, but is preferably 50 nm to 150 nm, and more preferably about 100 nm.

  As a material of the channel protective film 18 which is the second insulating layer, a transparent silicon oxide system or silicon nitride system can be used, but a silicon oxide system is desirable. Since the channel protective film 18 is in contact with IGZO, when silicon nitride is used as a channel protective film by the CVD method, nitrogen of ammonia used as one of the source gases is combined with oxygen in the IGZO to convert oxygen in the IGZO. It tends to be deficient, and the characteristics of IGZO tend to change. Such inconvenience does not occur if the silicon oxide system is used, and the composition of IGZO can be maintained by using the silicon oxide system. The channel protective film 18 is formed so as to cover the entire surface of the substrate. As a result, the semiconductor layer 14 is covered with the channel protective film 18. The film thickness may be about 200 nm or thinner.

  The source electrode 25 and the drain electrode 26 are patterned from the second metal layer. The material or structure of the second metal layer is not particularly limited, and may be a single layer film of Al or Mo. However, in the case where wirings such as signal lines of the display device are also formed by the second metal layer, the upper layer is made of ITO. When a transparent conductive layer such as ITO is likely to be formed, a laminated structure is desirable in order to avoid electrolytic corrosion between ITO or the like and Al. For example, it is desirable to use a laminated film (laminated wiring) formed by combining Al and Mo, such that the upper layer in contact with ITO is Mo and the lower layer is Al.

  In addition, when an oxide semiconductor is used as the material of the semiconductor layer, particularly when IGZO is used as the semiconductor layer, IGZO has similar chemical characteristics to ITO, so that the same is true at the interface between IGZO and Al. In order to avoid the problem of electric corrosion, when connecting Al and ITO or IGZO, a metal layer having a three-layer structure such as Mo-Al-Mo is used, and ITO or IGZO is connected to Al via Mo. Such a structure is desirable. As described above, by using the second metal layer in which the uppermost layer and the lowermost layer are made of a metal containing Mo, Mo functions as a so-called cover metal to prevent the electrolytic corrosion reaction, and the lower layer of the second metal layer is oxidized. Prevents galvanic corrosion between Al and oxide semiconductor layers and between Al and ITO and other transparent conductive layers even when connected to a physical semiconductor and the upper layer is connected to a transparent conductive layer such as ITO. In addition, a good ohmic contact can be obtained with a low resistance, and a good and highly reliable electrical connection can be made. The thickness of the second metal layer is 200 nm to 400 nm, more preferably 300 nm.

  The material of the passivation layer 19 that is the third insulating layer is not particularly limited, and silicon nitride or the like having insulation and transparency can be used. The thickness of the passivation layer is 200 nm to 500 nm. The passivation layer 19 is formed so as to cover the entire surface of the substrate. As a result, the source electrode 25 and the drain electrode 26 formed from the second metal layer are covered with the passivation layer 19.

[Production method]
Next, with reference to FIG. 1, the manufacturing method of TFT concerning this Embodiment is demonstrated in order of a process. This figure is an explanatory view of a manufacturing process of a TFT or the like according to an embodiment of the present invention. First, as shown in FIG. 1A, a first metal layer is formed on a substrate 11 and patterned to form a gate electrode 12 (first step). A method for forming the first metal layer is not particularly limited, but a sputtering method may be used. The material and structure of the first metal layer are as described above. If necessary, a wiring pattern such as a scanning line 72 (FIG. 3) may be formed in this step.

  Next, the gate insulating film 13 is formed on the entire surface of the substrate by a CVD method or the like (second step). As a result, the gate electrode 12 is covered with the gate insulating film 13. As a formation method, a CVD method is desirable, and a thermal CVD method, a plasma CVD method, or the like can be used. When it is desired to suppress an increase in the substrate temperature, for example, when a plastic substrate is used, the substrate temperature at the time of forming the gate insulating film is desirably about 250 ° C. or less, and it may be formed by a plasma CVD method. it can.

  Next, a semiconductor layer is formed (third step). A method for forming the semiconductor layer is not particularly limited, but a sputtering method is desirable. By using the sputtering method to form the IGZO semiconductor layer, it is possible to control the conductivity, carrier concentration, mobility, etc. to some extent by controlling the gas flow rate during film formation and the partial pressure of oxygen in the film formation atmosphere. Thus, it is possible to form a film with a more stable composition. In addition, when an amorphous IGZO semiconductor layer is formed on a plastic substrate, a sputtering method is preferable in consideration of the heat resistance of the substrate and reducing damage to the substrate.

As a sputtering target, solid InGaZnO ₄ containing In, Ga, Zn, and O (oxygen) is used. The composition ratio (stoichiometry) represented by the molecular formula of InGaZnO ₄ is In: Ga: Zn: O = 1: 1: 1: 4, but Zn and oxygen are poorer than this. For example, an oxide in which In: Ga: Zn: O is 1: 1: 0.5: 3.5 can also be used as a target before film formation. The semiconductor layer after film formation is a transparent amorphous semiconductor layer, and the composition ratio of each component of In, Ga, Zn, and O is not limited to 1: 1: 1: 4, but is approximately 1: 1: 0.5: As in 2, Zn or oxygen may be poor. In the present invention, the term “amorphous” does not mean only a completely amorphous state, but also includes those containing microcrystals as long as the gist of the present invention is not impaired.

  The formed amorphous IGZO semiconductor layer is patterned by a photolithography method or an etching method. Thereby, the semiconductor layer 14 of the TFT 20 made of amorphous IGZO is formed. The semiconductor layer 14 has a single island shape, and is formed into three regions, that is, a source region 15, a drain region 16, and a channel region 17 of the TFT 20 by ultraviolet irradiation in a subsequent process.

  Although the etchant of the semiconductor layer 14 is not particularly limited, it is possible to use an etchant of ITO such as oxalic acid regardless of before and after irradiation with ultraviolet rays because the chemical property of IGZO is similar to that of ITO. it can. Succinic acid does not etch Al, but can etch ITO and IGZO. Since the ITO etchant can also be used as the IGZO etchant, the TFT manufacturing process can be simplified. The etching temperature may be around room temperature. Next, as shown in FIG.1 (b), the ultraviolet-ray 22 is irradiated (4th step, FIG.1 (b)). As an irradiation method, for example, ultraviolet light is applied from the direction of the gate electrode 12 toward the semiconductor layer 14, that is, from the back surface of the substrate 11 toward the gate electrode 12 and the semiconductor layer 14, using the light-shielding gate electrode 12 as a shadow mask. 22 is irradiated (backside irradiation).

  As described above, the semiconductor layer 14 can be selectively irradiated with ultraviolet rays by irradiating the semiconductor layer 14 with the gate electrode 12 as a shadow mask. In this embodiment mode, since a transparent amorphous oxide made of IGZO is used as a material of the semiconductor layer of the TFT, the conductivity of the semiconductor layer can be improved by irradiating it with ultraviolet rays 22. Then, by selectively irradiating a part of the semiconductor layer with such ultraviolet rays, the conductivity can be increased only in the irradiated region. Accordingly, by selectively irradiating the regions of the semiconductor layer 14 of the TFT 20 that should become the source region 15 and the drain region 16 with ultraviolet rays, the source region 15 and the drain region 16 having a conductivity that can be used as electrodes are configured. can do. Therefore, it is not necessary to separately form a low-resistance semiconductor layer such as the n + amorphous silicon layer of the conventional example in order to connect the source electrode 25 and the drain electrode 26 made of metal to the source region 15 and the drain region 16, respectively. On the other hand, the conductivity of the region of the semiconductor layer that has not been irradiated with ultraviolet rays is maintained as it was before the irradiation, so that the region that should become the channel region 17 of the TFT is not irradiated with ultraviolet rays. By doing so, the region becomes a region having conductivity that can be used as a channel of the TFT. Details of the relationship between ultraviolet irradiation and conductivity will be described later.

  Then, as described above, by using the gate electrode 12 as a shadow mask and irradiating the back surface with the ultraviolet ray 22, the three regions of the source region 15, the drain region 16 and the channel region 17 having the conductivity before the ultraviolet ray irradiation are made highly conductive. Are formed in a self-aligned manner with respect to the gate electrode 12 (self-alignment). The irradiated ultraviolet rays may enter the inside of the gate electrode by dimensions Ls2 and Ld2 from the side edge of the gate electrode 12 due to the influence of diffraction of the ultraviolet rays and the like. Each region 16 is formed to extend in the center direction of the channel region 17 by this dimension. Therefore, in such a case, the TFT 20 having a channel length L that is shorter by Ls2 and Ld2 than the dimension Lg of the gate electrode 12 in the channel length direction is formed in a self-aligned manner. When the influence of diffraction or the like is small, Ls2 and Ld2 are substantially zero μm, and the channel length L is substantially the same as Lg. Therefore, it can be said that the TFT 20 having the channel length L which is the same as the dimension Lg of the gate electrode 12 in the channel length direction or shorter than the dimension Lg by Ls2 and Ld2 is formed in a self-aligned manner. The channel length L of the TFT 20 can be said to be the same as the dimension between the highly conductive source region 15 and drain region 16. In either case, a thin film transistor having a short channel length and a small Cgs and Cgd can be manufactured.

  In the TFT 20 formed in this way, the overlap between the gate electrode 12 and the source region 15 or the drain region 16 in a plan view is only a portion of the dimensions Ls2 and Ld2, and this Ls2 and Ld2 is about 0.5 μm or less. Since it is 1 μm or less, Cgs1 and Cgd1 generated by the overlap are extremely small. In addition, since the source region 15 and the drain region 16 formed in this way are formed in a self-aligned manner with respect to the gate electrode 12, variations in Ls2 and Ld2 are extremely small. As a result, Cgs1 and Cgd1 The variation of is very small.

  Further, as described above, the highly conductive source region 15 and drain region 16 are formed in a self-aligned manner, and the source region 15 and drain region 16 and the channel region 17 are always electrically connected. As in the conventional example, the distance between the source electrode 25 and the drain electrode 26 and the distance between the n + amorphous silicon layers 24s and 24d are equal to or larger than the minimum processing dimension F, and even if there is a mask alignment shift, The restriction that the drain electrode 26 and the n + amorphous silicon layers 24s and 24d must be connected to the end of the channel region 17 is solved. Therefore, in the present invention, the dimension Lg of the gate electrode 12 in the channel length direction is about the minimum processing dimension F, and does not need to be increased to about three times the minimum processing dimension F as in the prior art. Therefore, the channel length L of the TFT of the present invention is also the same as Lg or shorter than Lg by Ls2 and Ld2, and the channel length L is approximately 1/3 of the conventional size, that is, substantially the same as the minimum processing dimension F or The dimension is shorter than F by Ls2 and Ld2. As a result, Cgs2, which is determined by the channel length of Cgs, is reduced to about ３ compared to the conventional case. Further, since it is not affected by the mask misalignment of the source electrode 25 and the drain electrode 26 with respect to the gate electrode 12 as in the conventional example, the in-plane variation of Cgs2 itself is reduced. The same applies to Cgd2 that contributes to the gate-drain parasitic capacitance.

  Thus, since the magnitude | size and dispersion | variation of Cgs1 and Cgs2 become small, the magnitude | size and variation of the gate-source parasitic capacitance Cgs become also extremely small. The same applies to the parasitic capacitance Cgd between the gate and the drain. As a result, when such a TFT is used in, for example, a liquid crystal display device, the punch-through voltage due to Cgs is also reduced and uniformed, and display quality can be improved. Unevenness is significantly reduced. This also reduces the recharging effect, reduces the luminance gradient phenomenon, and improves the display quality. In addition, since the Cgs value itself is reduced and the variation thereof is reduced, the storage capacitor Cs can also be reduced from the viewpoint of measures against Cgs. Accordingly, the area of the electrode made of a light-shielding metal constituting the storage capacitor Cs can be reduced, so that the aperture ratio of the pixel portion is improved.

  Next, the conditions for ultraviolet irradiation will be described in more detail. First, in the ultraviolet irradiation process, at least the semiconductor layer 14 is formed, the semiconductor layer to be the source region 15 and the drain region 16 is not shielded, and the gate electrode 12 serving as a shadow mask is the channel region 17. If it is formed at a position to be, irradiation can be performed in subsequent steps as long as the gist of the present invention is not impaired. In this embodiment, it is described that ultraviolet irradiation is performed after the patterning of the semiconductor layer 14 as described above. However, the patterning may be performed after the semiconductor layer is formed and before the patterning. It may be after formation.

  Next, the irradiation conditions such as the ultraviolet light source, wavelength, irradiation energy density, and irradiation time in the ultraviolet irradiation step are as follows. The ultraviolet light source to be irradiated is preferably a surface light source. Since a surface light source is used, it is possible to uniformly irradiate ultraviolet rays at once over a wide irradiation area that covers the entire substrate. In addition, since a surface light source is used, it is not necessary to scan the substrate as in the case of a laser light source with a narrow beam spot, so double irradiation of the semiconductor layer due to scanning and accompanying in-plane variations in TFT characteristics are also caused. Does not occur. Therefore, it is possible to irradiate ultraviolet rays with uniform irradiation energy. As a result, when a large number of TFTs are formed over the entire display screen of a large area, not only simplification of the process and improvement of mass productivity, A variation in characteristics can be suppressed and uniform, and a display device with high display quality and free from variations in luminance and luminance can be obtained.

  The ultraviolet light source may be a lamp that irradiates ultraviolet rays having a specific range of wavelengths instead of a laser light source. Since a laser light source is not used, it is possible to avoid problems due to heat generation of the substrate due to the laser light, and it is possible to use a plastic film substrate. Further, an ultraviolet irradiation device that is less expensive than a laser beam irradiation device can be used. Although the kind of lamp | ramp used as an ultraviolet light source is not specifically limited, For example, a mercury lamp can be used. The wavelength of the ultraviolet light to be irradiated is desirably a wavelength ranging from about 270 nm to about 450 nm. By irradiating ultraviolet rays in this wavelength range, the conductivity of the irradiated region can be improved. The temperature and irradiation atmosphere of the substrate at the time of ultraviolet irradiation are not particularly limited, but can be performed in the air at room temperature.

Next, the irradiation energy density of ultraviolet rays and the irradiation time will be described. FIG. 2 is a graph showing a relationship between the conductivity of the amorphous IGZO semiconductor layer and the ultraviolet irradiation time when the amorphous IGZO semiconductor layer is irradiated with ultraviolet rays having an irradiation energy density of 100 mJ / sec · cm ^2. . From the figure, it is recognized that the increase in conductivity is saturated when irradiated at an irradiation energy density of 100 mJ / sec · cm ² for about 6 hours or more. Until then, the irradiation time is 6 hours, and the conductivity is In sample # 1, 2 × 10 ¹ S / m, which is approximately 3.33 × 10 ⁵ times (= 10 ^5.52 times), compared to 6 × 10 ⁻⁵ S / m before irradiation, and in sample # 2 the same irradiation It is recognized that it is improved exponentially to 4 S / m, which is about 10 ⁷ times that of the previous 4 × 10 ⁻⁷ S / m. That the conductivity increases exponentially from about 3.33 × 10 ⁵ times (= 10 ^5.52 times) to about 10 ⁷ times in 6 hours of irradiation, in other words, about 0.86 to about This means that the conductivity increases about an order of magnitude every 1.09 hours.

As a measure of the irradiation time of ultraviolet rays, when the irradiation energy density is 100 mJ / sec · cm ² , the conductivity after ultraviolet irradiation (target conductivity) is improved to 10 ⁿ times the conductivity before ultraviolet irradiation. In general, the irradiation may be performed with 0.86 · n hours to 1.09 · n hours (provided that 0 <n ≦ 6) as a guide. This is equivalent to about (309 · n) J / cm ² to (392 · n) J / cm ² in terms of integrated irradiation energy density (= irradiation energy density × irradiation time). Since the conductivity depends on the cumulative irradiation energy density of ultraviolet rays, for example, if the same conductivity is obtained, the irradiation time may be ¼ if the irradiation energy density is quadrupled. Therefore, the irradiation energy density and the irradiation time can be easily set if the target conductivity is determined after measuring the conductivity before irradiation, and is made of amorphous IGZO having a desired conductivity by appropriate irradiation of ultraviolet rays. A semiconductor layer can be obtained.

For example, according to the figure, the conductivity can be improved to about 10 ⁻² S / m or more by irradiating with ultraviolet rays for about 3.7 hours (accumulated irradiation energy density of about 1332 J / cm ² ). Is recognized. Further, as in sample # 1, depending on the conductivity before ultraviolet irradiation, this level of conductivity is reached even in about 2.5 hours (accumulated irradiation energy density of about 900 J / cm ² ). And if it is such high conductivity, it can be functioned as a low resistance semiconductor layer like the n + amorphous silicon layer demonstrated by the prior art example. Note that a layer having a conductivity substantially equivalent to that of a metal can be formed by irradiating ultraviolet rays to a conductivity of about 10 ⁻¹ S / m to 1 S / m.

Note that the integrated irradiation energy density of the ultraviolet rays to be irradiated to the source region 15 and the drain region 16 is generally such a value that the resistance of the entire source region 15 or the entire drain region 16 is lower than the on-resistance of the TFT 20. It is desirable to do. Therefore, you may set the integrated irradiation energy density which should be irradiated from such a viewpoint. By doing in this way, the fall of signal levels, such as an image signal, by resistance of the whole source region or the whole drain region can be reduced. As shown in FIG. 1C, the distance between the source electrode 25 and the end of the channel region 17 is short, and the resistance from the source electrode 25 to the channel region 17 through the source region 15 is small. In addition, the conductivity of the source region 15 after the ultraviolet irradiation may be about 10 ⁻² S / m or less as long as it does not adversely affect the other. The same applies to the conductivity of the drain region 16.

  In this way, by selectively irradiating the region to be the source region 15 or the drain region 16 of the semiconductor layer 14 with ultraviolet rays, the conductivity can be controlled to a desired value. Therefore, in order to form the source region 15 or the drain region 16 having higher conductivity than the channel region 17, it is not necessary to perform impurity implantation by ion doping or the like as in the prior art, and the channel region 17, the drain region 16 and the source region are not required. The impurity concentration of 15 may be the same. Therefore, an expensive ion doping apparatus or the like is not required, and the manufacturing process can be rationalized, and damage to the semiconductor layer due to ion doping can be avoided. The cumulative irradiation energy density of ultraviolet rays also depends on the film thickness of the amorphous IGZO semiconductor layer, and generally requires a larger energy density as the film thickness increases.

  After the ultraviolet irradiation process in this way, as shown in FIG. 1C, a channel protective film 18 as a second insulating layer is formed on the entire surface of the substrate, and contact holes 23s and 23d are formed (fifth). Step). As a result, the semiconductor layer 14 is covered with the channel protective film 18, and contact holes 23 s and 23 d for connecting to the source region 15 and the drain region 16 can be formed. The contact holes 23 s and 23 d penetrate the channel protective film 18 and reach the source region 15 and the drain region 16, respectively. A method for forming the channel protective film 18 is not particularly limited, but a CVD method can be used. The material of the channel protective film 18 is as described above. As an etching method at this time, it is desirable to use a dry etching method using plasma.

  Next, a second metal layer is formed (sixth step). By patterning the second metal layer, the source electrode 25 and the drain electrode 26 made of the second metal layer are formed. The formation method is not particularly limited, but a sputtering method may be used. The material and structure of the second metal layer are as described above. Next, a passivation layer 19 as a third insulating layer is formed on the entire surface of the substrate by CVD using silicon nitride or the like. As a result, the second metal layer and the like are covered with the passivation layer 19 (seventh step, FIG. 1C). Through the above steps, the TFT 20 using the self-aligned bottom gate type IGZO as a semiconductor layer is formed.

[Concrete example]
Hereinafter, specific examples of the production method of the present invention will be described. A first metal layer was formed on the substrate 11. A stacked first metal layer having an AlNd layer as a lower layer and Mo as an upper layer was formed by sputtering, and patterned to form a gate electrode 12. The composition of the lower AlNd layer was Al containing about 2% Nd. This metal layer has light shielding properties. The thickness of the first metal layer was 300 nm. Next, the gate insulating film 13 was formed by plasma CVD. The substrate temperature during the formation of the gate insulating film 13 was set to 200.degree. The film thickness was 300 nm.

  Next, in forming the semiconductor layer 14, a sputtering method was used. The target used was an ingot in which the composition ratio of each component of In, Ga, Zn, and O was 1: 1: 1: 4. The input power of the sputtering apparatus was 0.5 kW. The substrate temperature during film formation was room temperature, the atmosphere was a total pressure of 0.265 Pa, and the oxygen partial pressure was 0.011 Pa. The gas flow rate during film formation was 67 sccm for Ar as a carrier gas, 22 sccm for Ar as a holder gas, and 4 sccm for oxygen. Note that sccm is an abbreviation for standard cc / min. The film formation rate is 43.2 nm / min. As a result, a transparent n-type amorphous IGZO semiconductor layer having a thickness of 100 nm could be formed on the glass substrate 11 having insulation and transparency.

As shown in FIG. 2, the electrical conductivity of this semiconductor layer is about 6 × 10 ⁻⁵ S / m to 4 × 10 ⁻⁷ S / m at room temperature, so that it can be used as the semiconductor layer 14 of the TFT. Note that a two-probe measurement method was used to measure the conductivity. The amorphous IGZO semiconductor layer formed in this way is patterned and formed into an appropriate size and shape by using a photolithography method and an etching method, and the TFT channel region 17, drain region 16, source region 15, A semiconductor layer 14 to be formed was formed. As the etchant, oxalic acid having a concentration of 3.2% was used. The etching temperature was 30 ° C.

  Next, ultraviolet rays were irradiated from the back surface of the substrate 11 toward the semiconductor layer 14 using the gate electrode 12 as a shadow mask. As a light source device, a UV irradiation device (model number UL750) manufactured by HOYA CANDEO OPTRONICS was used. This apparatus uses an ultrahigh pressure mercury lamp as a light source, and this lamp emits ultraviolet rays having a wavelength ranging from about 270 nm to about 450 nm. The temperature of the substrate 11 at the time of ultraviolet irradiation was room temperature, and the irradiation atmosphere was performed in the air. Note that after the film formation and before the ultraviolet irradiation step, annealing treatment at a special temperature in a special atmosphere was not performed. Neither laser irradiation nor ion doping was performed.

The ultraviolet irradiation energy density was 100 mJ / sec · cm ² . If it is this irradiation energy density, since it can irradiate using the general ultraviolet irradiation device used for the other use, rationalization of a manufacturing facility can be aimed at. When the irradiation time is about 3.7 hours (accumulated irradiation energy density is about 1332 J / cm ² ), the conductivity of the source region 15 and the drain region 16 can be improved to about 10 ⁻² S / m. It was.

When the stoichiometric ratio of the IGZO semiconductor layer after ultraviolet irradiation was analyzed using an XPS M-Probe analyzer XPS (X-ray photoelectron spectroscopy) manufactured by SSI, each component of In, Ga, Zn, and O was analyzed. The composition ratio was about 1: 1: 0.6: 3. Further, the IGZO semiconductor layers before and after the ultraviolet irradiation are both transparent, and when X-ray diffraction is performed at an incident angle of 1 degree using the Rigaku X-ray diffractometer RINT-2000, it can be seen in the InGaZnO ₄ crystal. No diffraction peak was observed, confirming that all were amorphous IGZO semiconductor layers.

  Next, a channel protective film 18 was formed, a contact hole 23 was formed by plasma dry etching, and a second metal layer was further formed. As the second metal layer, a metal layer having a three-layer structure of Mo—Al—Mo was used. After the formation of the second metal layer, the source electrode 25 and the drain electrode 26 were formed by patterning. Next, a passivation layer 19 was formed by CVD using silicon nitride. Through the above steps, an amorphous IGZO TFT 20 was formed.

[Display device]
The TFT and the manufacturing method thereof according to this embodiment can be used for a display device and a manufacturing method thereof. Such a display device includes, for example, a TFT 20 formed on a substrate that controls modulation of light by an electro-optical member, a pixel electrode to which a signal for controlling modulation is supplied from the TFT 20, and a gap between the pixel electrode and the counter electrode. And an electro-optical member provided for display. In addition, such a display device using a TFT that controls modulation of light by an electro-optical member includes, for example, a process of forming the TFT 20 on a substrate using the TFT manufacturing method according to the present embodiment, It can be manufactured by a manufacturing method including a step of forming a pixel electrode to which a signal for controlling modulation is supplied and a step of disposing an electro-optic member for display between the pixel electrode and the counter electrode.

  As described above, the TFT 20 according to the present embodiment can be used as an active element for controlling light modulation in a display device in which display is performed by an electro-optic member having a light modulation function. As such an electro-optical member, for example, a liquid crystal, an OLED (Organic Light Emitting Diode), a microcapsule related to electrophoresis, or the like can be considered. In such an electro-optical member, light is modulated by the value of voltage or current applied to the electro-optical member. For example, in the case of a liquid crystal, the transmitted light can be modulated by a combination with an optical member such as a polarizing plate, and in the case of an OLED that emits light by itself, the light emission can be modulated. In any case, such light modulation can be used for pixel gradation control. Therefore, the gradation can be controlled by controlling the voltage or current to be applied by the TFT according to the present embodiment, and various display devices by using such an electro-optical member as a member for display, For example, an EPID (ElectroPhoretic Image Display) such as a liquid crystal display device, an OLED display device, and electronic paper can be realized.

  As an embodiment of the display device, an active matrix liquid crystal display device using the TFT according to this embodiment will be described. In general, a liquid crystal display device includes a liquid crystal panel in which liquid crystal is disposed between a cell array substrate and a counter substrate. FIG. 3 is a schematic configuration diagram of a liquid crystal panel unit of the active matrix type liquid crystal display device according to the present embodiment. FIG. 3A is a schematic plan view of the cell array substrate 101, and FIG. 3B is an equivalent circuit diagram for explaining the functions of the pixel unit 10 and its peripheral members.

  The cell array substrate 101 is formed with a plurality of scanning lines 72 extending in the X (row) direction and connected to the scanning line external terminals 74 and the gate electrodes of TFTs serving as switching elements in the pixel unit 10. . A scanning signal which is a signal for selectively switching the TFT is supplied to the TFT via the scanning line 72. A plurality of scanning line external terminals 74 corresponding to the plurality of scanning lines 72 are provided in the Y direction near the end of the cell array substrate 101. The scanning line external terminal 74 is connected to a predetermined terminal (not shown) of the scanning line driving device 70 such as a scanning line driver IC via an ACF (anisotropic conductor) (not shown).

  In the cell array substrate 101, a plurality of signal lines 82 extending in the Y (column) direction and connected to the signal line external terminals 84 and the drain electrodes of the TFTs in the pixel portion 10 are formed. An image signal is supplied to the TFT selected by the scanning signal via the signal line 82. A plurality of signal line external terminals 84 corresponding to the plurality of signal lines 82 are provided along the X direction near the end of the cell array substrate 101. The signal line external terminal 84 is connected to a predetermined terminal (not shown) of the signal line driver 80 such as a signal line driver IC via an ACF (not shown). The scanning line driving device 70 and the signal line driving device 80 may be disposed on the cell array substrate 101. In FIG. 3A, a storage capacitor line 28 (described later), which is a common line for the storage capacitor Cs27, is not shown.

  The pixel units 10 are arranged in a matrix in a region defined by the scanning lines 72 and the signal lines 82 corresponding to the intersections of the scanning lines 72 and the signal lines 82 on the cell array substrate. The pixel unit 10 includes a TFT 20. The structure of the TFT 20 is as described above. The gate electrode 12 is electrically connected to the scanning line 72 in the pixel portion 10. The drain electrode 26 is electrically connected to the signal line 82 and the drain region 16. The source electrode 25 is electrically connected to the pixel electrode 32 and the source region 15.

  The storage capacitor Cs27 is formed between the pixel electrode 32 and the storage capacitor line 28 to which a predetermined voltage is applied. The storage capacitor Cs27 is applied during a period in which the TFT 20 is in an off state (non-selection period) after the voltage output from the signal line 82 is applied to the pixel electrode 32 via the TFT 20 in a period in which the TFT 20 is in an on state (selection period). This is a capacitance provided to maintain this applied voltage substantially constant for a required time. In addition, the storage capacitor line 28 is a wiring commonly connected to the storage capacitor Cs of each pixel portion in order to supply power to one electrode of the storage capacitor Cs27, and a storage capacitor common signal having a predetermined voltage is supplied. Is done.

  The common electrode (counter electrode) 34 is formed so as to face the pixel electrode 32 and is a transparent electrode common to each pixel. The common electrode 34 is generally formed on a counter substrate (not shown) in a TN (Twisted Nematic) type or VA (Vertical Alignment) type liquid crystal display device. A common signal having a predetermined voltage is applied to the common electrode 34 via a common electrode line (common electrode line) 35. Between the pixel electrode 32 and the counter electrode 34, the liquid crystal 99 which is an electro-optical member is provided. Reference numerals 38 and 39 are a gate-source parasitic capacitance Cgs and a gate-drain parasitic capacitance Cgd, respectively.

  The operation of the liquid crystal display device 100 including such a pixel unit 10 is, for example, as follows. The scanning line driving device 70 selects a pixel unit 10 to which the image signal from the signal line 82 should be written in units of rows based on a synchronization signal and other information of an image signal (not shown) input to the liquid crystal display device 100. Is output. Similarly, the signal line driving device 80 operates in synchronization with the scanning signal based on the luminance information of the image signal and supplies the image signal to the pixel unit 10 selected in the scanning period. Then, a voltage corresponding to the image signal from the signal line driving device 80 is applied to the pixel electrode 32 via the TFT 20 in the selected pixel unit 10. That is, an image signal which is a signal for controlling light modulation is supplied to the pixel electrode 32 from the source region 15 of the TFT 20 via the source electrode 25. As a result, an electric field is generated between a pair of electrodes including the pixel electrode 32 and the common electrode 34, and the orientation of the molecules of the liquid crystal 99 (the orientation of the liquid crystal molecules) is controlled by this electric field. Then, the display action of an image or the like is performed by modulating the light transmitted through the liquid crystal using this change in orientation. In this way, a liquid crystal display device is configured.

  A method for manufacturing such a liquid crystal display device will be described. The TFT 20 according to this embodiment is formed on the substrate 11 of the cell array substrate 101. The manufacturing method is as already described in the TFT manufacturing method. Then, after forming the passivation layer 19 on the TFT 20, if necessary, patterning is performed by etching, and removing a part thereof, for example, a transparent conductive layer made of ITO formed in the next step and A contact hole (not shown) for electrical connection is formed. Note that the scanning lines 72, the signal lines 82, and other necessary wirings can be formed in the PEP in which the gate electrode 12, the source electrode 15, or the drain electrode 16 is formed.

  Next, although not shown, a transparent conductive layer is formed by a sputtering method or the like. Although the material of a transparent conductive layer is not specifically limited, For example, ITO is used. After forming the transparent conductive layer, the pixel electrode 32 can be formed by patterning the transparent conductive layer. In this way, the cell array substrate 101 including various wirings such as the pixel portion 10 including the bottom gate TFT 20, the scanning line 72, and the signal line 82 on the substrate 11 is formed.

  Next, an alignment process or the like is performed on the cell array substrate 101 and a counter substrate provided with a color filter, and then both substrates are bonded together with a sealant. As the sealing material, for example, an ultraviolet curable sealing material such as a photo-curing acrylic resin is used. The liquid crystal display device 100 is completed by injecting liquid crystal between the liquid crystal substrates thus sealed and attaching optical members such as a drive circuit, a polarizing plate, and a backlight. Even in the case of FFS (Fringe Field Switching) type and IPS (In-Plane Switching) type liquid crystal display devices, there are structural differences such as the common electrode (counter electrode) provided on the cell array substrate. The present invention can be applied.

  In the case of an OLED display device, after the TFT according to this embodiment is formed on a substrate, a pixel electrode is formed, and an organic EL (organic electro luminescence) material as a light emitting layer is laminated together with other predetermined layers. By disposing this between the pixel electrode and the common electrode (counter electrode), an active matrix OLED display device can be realized. An image signal, which is a signal for controlling light modulation, is supplied to the pixel electrode from the source region or drain region of the TFT. In the case of an OLED display device, a plurality of TFTs (such as switching TFTs and driving TFTs) are generally used in one pixel portion. However, not only driving TFTs connected to pixel electrodes and driving organic EL, but also driving TFTs. The TFT according to this embodiment can also be used as a switching TFT for controlling the above. In other words, a signal for controlling light modulation supplied from the source region or drain region of the switching TFT that is not directly connected to the pixel electrode is connected to the source electrode or drain electrode of the driving TFT via the driving TFT. It can also be used in configurations such as those supplied to In general, the counter electrode is formed on a predetermined layer on the organic EL, that is, on the cell array substrate.

  The liquid crystal display device and the OLED display device thus manufactured can be used as a television receiver, a monitor for a personal computer, a mobile phone, an in-vehicle monitor, a game machine, and other flat panel displays. Note that the TFT according to this embodiment can also be used in an FED (Field Emission Display).

  In the case of EPID, an electrophoretic microcapsule containing, for example, positively charged white particles and negatively charged black particles is disposed between the pixel electrode and the counter electrode. Can be used as a display device by generating a predetermined electric field between them. Then, by supplying an image signal, which is a signal for controlling light modulation, from the source region or drain region of the TFT of the present invention to the pixel electrode, an active matrix display device is realized as in the case of the liquid crystal display device. be able to.

  Note that the TFT according to this embodiment is a bottom-gate TFT and has a configuration in which the gate electrode shields the TFT. Therefore, even when used in a liquid crystal display device, variation in TFT characteristics due to light from the backlight is small. In addition, since most amorphous silicon TFTs used in recent display devices adopt a bottom gate type, existing manufacturing processes, devices, equipment, etc. can be diverted in the practice of the present invention. Is possible.

  Note that FIG. 1 or FIG. 3 is merely a simplified illustration of the main members and relationships between the members related to the present embodiment in order to describe the present embodiment. In addition to those mentioned in the above description, many members are used to configure the TFT and the display device. However, they are well known to those skilled in the art and will not be described in detail here. In this embodiment mode, the TFT has been described as an example of a pixel portion of a display device. However, the TFT according to this embodiment mode includes, for example, a scanning line driving device and a signal line driving device other than the pixel portion. Even in a normal circuit or apparatus, it can be used as a switching element or an amplifying element. The display device described in this embodiment mode is merely an example, and other display devices are included in the scope of the present invention as long as those skilled in the art can arbitrarily select them. In addition, the present invention can be implemented in devices other than display devices such as various sensors such as a touch panel, an image scanner, or an X-ray detector panel.

  The present invention has been described with reference to the specific embodiments shown in the drawings, but the present invention is not limited to the embodiments shown in the drawings, and so far as long as the effects of the present invention are exhibited. It goes without saying that any known configuration can be employed.

DESCRIPTION OF SYMBOLS 10 ... Pixel part 11 ... Substrate 12 ... Gate electrode 13 ... Gate insulating film (1st insulating layer)
14, 14p ... Semiconductor layer 15, 15p ... Source region 16, 16p ... Drain region 17, 17p ... Channel region 18, 18p ... Channel protective film (second insulating layer)
19: Passivation layer (third insulating layer)
20, 20p ... TFT (Thin Film Transistor)
22 ... UV 23, 23s, 23d ... Contact hole 24, 24s, 24d ... n + amorphous silicon layer 25 ... Source electrode 26 ... Drain electrode 27 ... Storage capacitor Cs
32 ... Pixel electrode 34 ... Common electrode (counter electrode)
38 ... Parasitic capacitance between gate and source Cgs
39: Parasitic capacitance between gate and drain Cgd
72 ... Scanning line 82 ... Signal line 100 ... Liquid crystal display device 101 ... Cell array substrate

Claims (14)

A first step of forming a gate electrode having light shielding properties on a substrate;
A second step of forming a gate insulating film on the gate electrode;
A third step of forming a semiconductor layer made of an amorphous oxide containing In, Ga, and Zn on the gate insulating film;
And a fourth step of forming an amorphous source region or drain region having a higher conductivity than the semiconductor layer before irradiation by irradiating the semiconductor layer with ultraviolet rays using the gate electrode as a shadow mask. A method for manufacturing a thin film transistor. 2. The method of manufacturing a thin film transistor according to claim 1, wherein a dimension of the gate electrode in a channel length direction is a minimum processing dimension. 3. The method for manufacturing a thin film transistor according to claim 1, wherein a resistance of the source region or the drain region after the irradiation with the ultraviolet light is lower than an on-resistance of the thin film transistor. 4. The method of manufacturing a thin film transistor according to claim 1, wherein the impurity concentration of the channel region of the semiconductor layer is the same as the impurity concentration of the source region or the drain region. 5. The method of manufacturing a thin film transistor according to claim 1, wherein the light source for irradiating the ultraviolet light is a surface light source. 6. The method of manufacturing a thin film transistor according to claim 1, wherein the light source for irradiating ultraviolet rays is a mercury lamp. 7. The method of manufacturing a thin film transistor according to claim 1, wherein the wavelength of the ultraviolet ray ranges from 270 nm to 450 nm. The cumulative irradiation energy density of ultraviolet rays in the fourth step is (309 · n) to (392 · n) J / cm ² when the conductivity is increased 10 ⁿ times (where 0 <n ≦ 6). A method of manufacturing a thin film transistor according to any one of claims 1 to 7, wherein: 9. The method of manufacturing a thin film transistor according to claim 1, wherein an integrated irradiation energy density of ultraviolet rays in the fourth step is 1332 J / cm ² or more. 10. The method of manufacturing a thin film transistor according to claim 1, wherein an irradiation energy density of ultraviolet rays in the fourth step is 100 mJ / sec · cm ² . Forming a thin film transistor using the method of manufacturing a thin film transistor according to any one of claims 1 to 10;
And a step of arranging an electro-optic member for controlling display of light by the thin film transistor and providing the display. 12. The method of manufacturing a display device according to claim 11, wherein the electro-optical member is a liquid crystal. A gate electrode having a light shielding property formed on the substrate;
A gate insulating film formed on the gate electrode;
A channel region, and an amorphous source region or drain region whose conductivity is higher than before irradiation by irradiating the semiconductor layer with ultraviolet light using the gate electrode as a shadow mask, and on the gate insulating film And a semiconductor layer formed of an amorphous oxide containing In, Ga, and Zn. A thin film transistor according to claim 13,
A display device comprising: an electro-optic member for controlling display of light modulated by the thin film transistor;

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