WO2012056933A1 - Dispositif à oxyde semi-conducteur et son procédé de fabrication - Google Patents

Dispositif à oxyde semi-conducteur et son procédé de fabrication Download PDF

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Publication number
WO2012056933A1
WO2012056933A1 PCT/JP2011/073879 JP2011073879W WO2012056933A1 WO 2012056933 A1 WO2012056933 A1 WO 2012056933A1 JP 2011073879 W JP2011073879 W JP 2011073879W WO 2012056933 A1 WO2012056933 A1 WO 2012056933A1
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oxide semiconductor
semiconductor layer
amorphous oxide
layer
semiconductor device
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PCT/JP2011/073879
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English (en)
Japanese (ja)
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裕紀 若菜
哲史 河村
内山　博幸
藤井　邦治
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株式会社日立製作所
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Priority to JP2012540783A priority Critical patent/JP5666616B2/ja
Publication of WO2012056933A1 publication Critical patent/WO2012056933A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous

Definitions

  • the present invention relates to a semiconductor device having a thin film transistor (TFT: Thin Film Transistor) using an oxide semiconductor material for a channel layer, and a technology effective when applied to the manufacture thereof.
  • TFT Thin Film Transistor
  • TFTs Thin film transistors
  • a processing temperature is 350 ° C. or higher, and thus a usable substrate material is limited.
  • glass substrates and flexible resin substrates often have a heat-resistant temperature of 350 ° C. or lower, and it is difficult to form thin film transistors on these substrates using a conventional semiconductor device manufacturing process.
  • a thin film transistor using an oxide semiconductor material that can be formed at a low temperature as a channel layer is underway.
  • this oxide semiconductor film is used for a channel layer
  • a thin film transistor can be formed over a glass substrate or a flexible resin substrate, so that a novel device that is not conventionally used can be manufactured at low cost.
  • a device can be formed using the transparency of the oxide semiconductor material, and the thin film transistor can be applied to an RFID (Radio Frequency Identification) tag or the like.
  • RFID Radio Frequency Identification
  • Patent Document 1 A method of sandwiching layers (Patent Document 1) and a method of forming low-resistance crystal grains having a composition different from that of the oxide semiconductor layer in the oxide semiconductor layer below the source and drain electrodes are proposed (Patent Document 2). Has been.
  • Patent Document 1 in which a low-resistance layer is sandwiched between an oxide semiconductor layer and source and drain electrodes, the low-resistance layer has a lower oxygen concentration in the film than the oxide semiconductor layer and includes crystal fine particles. It has been reported that a good contact can be formed by using a semiconductor layer. However, since it is difficult to form the oxide semiconductor layer and the low resistance layer at the same time in this method, an increase in manufacturing cost accompanying an increase in the number of manufacturing steps is a problem.
  • Patent Document 2 in which low-resistance crystal grains are formed in an oxide semiconductor layer, for example, in an oxide semiconductor layer made of In (indium) -Zn (zinc) -Ga (gallium) -O (oxygen). It has been reported that contact resistance is reduced by forming metal crystal grains having a diameter of about 20 nm. However, in the case of this method, a threshold voltage shift or an on-current (Ion) due to a larger number of crystal grains in the oxide semiconductor layer being formed in the vicinity of the gate insulating film than in the vicinity of the source and drain electrodes. / Reduction of off-current (Ioff) ratio is a problem.
  • An object of the present invention is to reduce a contact resistance between an oxide semiconductor layer and a source / drain electrode without causing a problem as in the prior art in a thin film transistor using an oxide semiconductor material for a channel layer. It is to provide a technology that can be used.
  • An oxide semiconductor device which is a preferable embodiment of the present invention includes a thin film transistor in which a gate electrode, a gate insulating film, an amorphous oxide semiconductor layer constituting a channel layer, a source, and a drain electrode are stacked in this order on an upper surface of a substrate. And the amorphous oxide semiconductor layer in the vicinity of the interface with the source and drain electrodes has crystal grains containing the constituent elements of the amorphous oxide semiconductor layer.
  • the crystal grains are formed by using energy of accelerated particles incident on the amorphous oxide semiconductor layer when depositing conductive films for source and drain electrodes on the amorphous oxide semiconductor layer.
  • a thin film transistor with low contact resistance between the oxide semiconductor layer and the source and drain electrodes can be realized.
  • the contact resistance between the oxide semiconductor layer and the source and drain electrodes can be reduced without increasing the number of manufacturing steps of the thin film transistor.
  • FIG. 3 is a cross-sectional view showing a method for manufacturing the thin film transistor continued from FIG. 2.
  • FIG. 4 is a cross-sectional view showing a method for manufacturing the thin film transistor following FIG. 3.
  • FIG. 5 is a cross-sectional view showing a method for manufacturing the thin film transistor continued from FIG. 4.
  • FIG. 6 is a cross-sectional view showing a method for manufacturing the thin film transistor continued from FIG. 5.
  • FIG. 7 is an enlarged view of FIG. 6.
  • FIG. 7 is a cross-sectional view showing a method for manufacturing the thin film transistor following FIG. 6.
  • FIG. 14 is a cross-sectional view showing a method for manufacturing the thin film transistor continued from FIG. 13.
  • FIG. 20 is a schematic diagram of an active matrix liquid crystal display device to which the array shown in FIG. 19 is applied.
  • the bottom gate means a structure in which the gate electrode is arranged below the channel layer (oxide semiconductor layer), and the top contact means that the source electrode and the drain electrode are arranged above the channel layer. Means the structure.
  • the bottom gate / top contact type thin film transistor of this embodiment is manufactured by the following method.
  • an insulating substrate 10 is prepared.
  • the material of the substrate 10 include Si (silicon), sapphire, quartz, glass, and a flexible plastic film.
  • the plastic film material include polyethylene terephthalate, polyethylene naphthalate, polyetherimide, polyacrylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate.
  • what provided the insulating coating layer on the surface of the above-mentioned material as needed can also be used.
  • a gate electrode 11 is formed by depositing a conductive film on the upper surface of the substrate 10 and then patterning the conductive film.
  • the conductive film constituting the gate electrode 11 Mo (molybdenum), Cr (chromium), W (tungsten), Al (aluminum), Cu (copper), Ti (titanium), Ni (nickel), Ta (tantalum)
  • a single layer film of metal such as Ag (silver), Co (cobalt), Zn, Au (gold), and Pt (platinum), an alloy film containing two or more of these metals, and a laminated film of these metals can do.
  • conductive metal oxide films such as ZnO (zinc oxide) to which ITO (In—Sn—O: indium tin oxide), Al, Ga, In, or B (boron) is added, and their conductivity
  • ITO In—Sn—O: indium tin oxide
  • Al Al
  • Ga In
  • B boron
  • a laminated film of a metal oxide and the metal can also be used.
  • a single layer film of conductive metal nitride such as TiN (titanium nitride), a laminated film of the conductive metal nitride and the metal, or the like can also be used.
  • a gate insulating film 12 is formed on the upper surface of the substrate 10 on which the gate electrode 11 is formed.
  • the insulating film constituting the gate insulating film 12 includes a silicon oxide film, a silicon nitride film, an aluminum oxide film, an aluminum nitride film, a Y 2 O 3 (yttrium oxide) film, an HfO 2 (hafnium oxide) film, and a YSZ (yttria stable). Zirconia) film, organic polymer insulating film, and the like.
  • Materials for organic polymer insulating films include polyimide derivatives, benzocyclobutene derivatives, photoacryl derivatives, polystyrene derivatives, polyvinyl phenol derivatives, polyester derivatives, polycarbonate derivatives, polyester derivatives, polyvinyl acetate derivatives, polyurethane derivatives, polysulfone derivatives. Acrylate resin, acrylic resin, epoxy resin, parylene and the like. These insulating films are deposited by a CVD method, a sputtering method, a vapor deposition method, a coating method, or the like.
  • the amorphous oxide semiconductor layer 13 is a semiconductor layer that constitutes a channel layer of the thin film transistor, and includes In, Zn, Cd (cadmium), Al, Ga, Si, Sn, Ce (cerium), Ge (germanium), and Hf.
  • An oxide in which one or more elements are combined with oxygen can be exemplified.
  • the oxide film constituting the amorphous oxide semiconductor layer 13 is deposited by sputtering, CVD, pulsed laser deposition (PLD), coating, printing, co-evaporation, or the like. The thickness is about 25 nm to 100 nm.
  • impurities may be doped as necessary, or the substrate 10 may be annealed. Further, the patterning of the oxide film is performed by dry etching or wet etching using a photoresist film as a mask.
  • a multi-source sputtering apparatus capable of simultaneously depositing Zn, Sn, and O is used, the gas pressure is set to 0.5 Pa (Ar (argon) + 10% O 2 ), the RC power is set to 50 W, and the room temperature is set.
  • an amorphous Zn—Sn—O (zinc tin oxide) film having a thickness of 50 nm was deposited on the gate insulating film 12.
  • the Zn—Sn—O film is patterned by wet etching using a photoresist film as a mask, and the Zn—Sn—O film is left in the region above the gate electrode 11 and the region in the vicinity thereof.
  • An oxide semiconductor layer 13 was formed.
  • an insulating film is deposited on the amorphous oxide semiconductor layer 13, and then the insulating film is patterned to thereby form a channel layer region (region above the gate electrode 11).
  • a barrier layer 15 is formed on the top.
  • Examples of the insulating film constituting the barrier layer 15 include inorganic insulating films such as a silicon oxide film, a silicon nitride film, and an alumina film, and organic insulating films such as a parylene film. These insulating films are deposited by a CVD method, a sputtering method, a coating method, or the like. The insulating film is patterned by dry etching or wet etching using a photoresist film as a mask.
  • a conductive film 14 is deposited on the amorphous oxide semiconductor layer 13 and the barrier layer 15.
  • Examples of the conductive film 14 include various conductive films that constitute the gate electrode 11 described above.
  • the conductive film 14 is deposited by electron beam evaporation, sputtering, or the like.
  • the conductive film 14 made of Al is deposited by using an electron beam evaporation apparatus and setting the acceleration voltage of the electron beam to a value higher than usual (for example, 10 kV).
  • a source electrode 14s and a drain electrode 14d are formed by removing the conductive film 14 above the gate electrode 11 by dry etching using a photoresist film as a mask.
  • a photoresist film as a mask.
  • a solid line A in FIG. 9 is a graph showing the relationship between the gate voltage (Vg) and the drain current (Id) of the thin film transistor manufactured by the above-described method.
  • a broken line B in the figure shows the relationship between the threshold gate voltage (Vg) and the drain current (Id) of the thin film transistor (comparative example) in which the conductive film 14 is deposited with the electron beam acceleration voltage set to 5 kV. It is a graph.
  • the channel length of the two types of thin film transistors was 0.1 mm, and the channel width was 2 mm.
  • the thin film transistor of this embodiment in which the conductive film 14 is deposited with the acceleration voltage of the electron beam set to 10 kV is 2 in comparison with the thin film transistor of the comparative example in which the acceleration voltage of the electron beam is set to 5 kV.
  • the on-current (Ion) was doubled or more.
  • FIG. 10 is a cross-sectional TEM photograph of the vicinity of the interface between the drain electrode 14d and the amorphous oxide semiconductor layer 13 in the thin film transistor of the present embodiment. As shown in FIG. 10, it was confirmed that the crystal grains 13cg were present in almost one row in the crystal grain existence region (Tcg) within a depth of 10 nm from the interface with the drain electrode 14d. On the other hand, the presence of the crystal grains 13cg could not be confirmed from the cross-sectional TEM photograph of the thin film transistor of the comparative example.
  • the deposition conditions of the conductive film (Al film) 14 constituting the source electrode 14s and the drain electrode 14d and the annealing conditions after the deposition was changed to change the grain size of the crystal grains 13cg and the crystal grain existence region (Tcg).
  • the on-current (Ion) was improved when the grain size of the crystal grain 13cg was about 15 nm and the crystal grain existence region (Tcg) was within 20 nm from the surface of the amorphous oxide semiconductor layer 13.
  • the grain size of the crystal grain 13cg exceeds 20 nm, the crystal grain 13cg starts to grow in a columnar shape, the surface roughness of the amorphous oxide semiconductor layer 13 occurs, and the contact resistance increases.
  • the grain size of the crystal grains 13cg is preferably 15 nm or less. Further, the crystal grain existence region (Tcg) is preferably within 20 nm from the surface of the amorphous oxide semiconductor layer 13, more preferably within 10 nm.
  • the contact resistance between the amorphous oxide semiconductor layer 13, the source electrode 14s, and the drain electrode 14d can be reduced. Accordingly, an on-current (Ion) is improved and field effect mobility is improved, so that a high-performance thin film transistor can be provided. Thereby, for example, an RFID tag that operates in a 13.56 MHz band can be realized.
  • the crystal grains 13cg are formed in the amorphous oxide semiconductor layer 13 only by setting the acceleration voltage of the electron beam to a value higher than usual. Since it forms, the special process and apparatus for forming the crystal grain 13cg are unnecessary.
  • the thin film transistor can also be manufactured by the following method. First, as shown in FIG. 12, the gate electrode 11, the gate insulating film 12, and the amorphous oxide semiconductor layer 13 are formed in this order on the upper surface of the insulating substrate 10. The steps so far are the same as the steps shown in FIGS. 1 to 4 of the first embodiment.
  • a conductive film 14 is deposited on the amorphous oxide semiconductor layer 13.
  • the conductive film 14 include various conductive films that constitute the gate electrode 11 described above.
  • the conductive film (Al film) 14 is deposited using a sputtering apparatus with the voltage applied between the substrate 10 and the conductive film material (target) set to a value higher than usual.
  • assist ions for example, Ar +
  • the assist ions collide with the surface of the amorphous oxide semiconductor layer 13 at a high speed.
  • the crystal grains 13cg can also be formed.
  • the surface of the amorphous oxide semiconductor layer 13 is irradiated with a high-energy laser beam.
  • the crystal grains 13cg can be formed.
  • the crystal grain 13cg preferably has a particle size of 15 nm or less. Further, the crystal grain existence region (Tcg) is preferably within 20 nm from the surface of the oxide semiconductor layer 13, and more preferably within 10 nm.
  • the source electrode 14s and the drain electrode 14d are formed by removing the conductive film 14 above the gate electrode 11 by dry etching using the photoresist film 16 as a mask.
  • the amorphous oxide semiconductor layer 13 therebelow is over-etched to remove the crystal grains 13cg formed near the surface of the channel layer region.
  • the bottom gate / top contact type thin film transistor of this embodiment is completed through the steps so far.
  • the thin film transistor has a channel length of 0.1 mm and a channel width of 2 mm.
  • the thin film transistor of this embodiment exhibited an on-current (Ion) that is twice or more that of the thin film transistor of the comparative example.
  • the constituent element of the crystal grain 13cg is not only the same as the constituent element of the amorphous oxide semiconductor layer 13, but may be at least a part of the constituent element of the amorphous oxide semiconductor layer 13.
  • the present embodiment it is possible to provide a high-performance thin film transistor, as in the first embodiment. Further, in this embodiment, the step of forming the barrier layer 15 on the channel layer region of the amorphous oxide semiconductor layer 13 is not necessary, so that a high-performance thin film transistor can be manufactured with fewer steps.
  • the amorphous oxide semiconductor layer 13 below the conductive film 14 is over-etched so that the surface of the channel layer region is near the surface. Crystal grains 13cg were removed. However, at this time, if the amount of overetching of the amorphous oxide semiconductor layer 13 varies, the film thickness of the channel layer varies, and the characteristics of the thin film transistor may vary.
  • the amorphous oxide semiconductor layer 13 has a stacked structure of a first oxide semiconductor layer 13 ⁇ / b> A and a second oxide semiconductor layer 13 ⁇ / b> B.
  • the layer 13A is made of an oxide of an element that can use s-orbital electrons as carriers, such as In or Sn.
  • the upper second oxide semiconductor layer 13B to be over-etched is made of a high resistance oxide having an oxygen concentration higher than that of the oxide constituting the lower first oxide semiconductor layer 13A.
  • the lower first oxide semiconductor layer 13A is made of SnOx
  • the upper second oxide semiconductor layer 13B is made of ZnSnOx.
  • the lower first oxide semiconductor layer 13A having a lower electrical resistance than the upper second oxide semiconductor layer 13B substantially functions as a channel layer, so that the upper second oxide semiconductor layer 13B Even if the amount of overetching varies, variation in characteristics of the thin film transistor can be suppressed.
  • FIG. 16 is a cross-sectional view illustrating the thin film transistor of this embodiment.
  • the thin film transistor of this embodiment is characterized in that crystal grains 13cg are formed not only in the vicinity of the interface between the source electrode 14s and the drain electrode 14d but also in the channel layer of the amorphous oxide semiconductor layer 13.
  • the manufacturing method of the thin film transistor of this embodiment is almost the same as the manufacturing method of Embodiment 2 described above.
  • the conductive film 14 for the source and drain electrodes is patterned by dry etching, the amorphous structure under the conductive film 14 is formed.
  • the only difference is that the oxide semiconductor layer 13 is not over-etched.
  • FIG. 17 is a graph showing the relationship between the threshold gate voltage (Vg) and the drain current (Id) of the thin film transistor of this embodiment.
  • the solid line C is obtained when the film thickness (tch) of the amorphous oxide semiconductor layer 13 is 10 nm or less (here, 6 nm), and the broken line D is the film thickness (tch) of the amorphous oxide semiconductor layer 13. ) Is thicker than 10 nm.
  • the film thickness (tch) of the amorphous oxide semiconductor layer 13 is 10 nm or less, a good on-current (Ion) value is shown, and compared with a conventional thin film transistor that does not form crystal grains 13 cg in the amorphous oxide semiconductor layer 13.
  • the on-current (Ion) more than twice. Further, when a cross-sectional TEM photograph in the vicinity of the channel layer of this thin film transistor was observed, crystal grains 13cg having a grain size of 5 nm or less were confirmed.
  • the film thickness (tch) of the amorphous oxide semiconductor layer 13 is greater than 10 nm, the amorphous oxide semiconductor layer 13 cannot be turned off even when the gate voltage is ⁇ 50 V, and behaves like a conductive film.
  • the film thickness (tch) of the amorphous oxide semiconductor layer 13 is 10 nm or less, even when the crystal grain 13cg is formed in the channel layer, the on-current (Ion) is improved, and the field effect It can be seen that the mobility is improved.
  • FIG. 18 shows a schematic configuration of an RFID tag 20 in which an antenna resonance circuit 21, a rectifier 22, a modulator 23, a digital circuit 24, and the like are configured using the thin film transistor of the present invention.
  • the RFID tag 20 can communicate with an external reader / writer 25 wirelessly using a high frequency of 13.56 MHz, for example. Further, since the oxide semiconductor layer constituting the channel layer of the thin film transistor is a transparent material, an almost transparent circuit can be formed in the IC chip.
  • a transparent wireless IC tag that transmits and receives at a high frequency (RF) of 13.56 MHz, for example, by configuring electrodes and wiring of an IC chip with a transparent conductive film such as ITO and circuit elements with the thin film transistor of the present invention.
  • RF high frequency
  • Such a wireless IC tag is different from a conventional RFID tag in that an IC chip and an antenna are almost transparent. Therefore, when the wireless IC tag is attached to a film or a card, the design printed on the film or the card is not damaged. .
  • FIG. 19 is a circuit block diagram showing an example of an array configuration of a semiconductor device using the thin film transistor of the present invention.
  • the semiconductor device of this embodiment has a configuration in which elements including the thin film transistor of the present invention are arranged on a substrate 30 in an array.
  • the thin film transistor is used as a switching transistor or a driving transistor for each element in the array, as well as a gate line driving circuit 32 for sending a signal to the gate wiring 31 connected to the gate electrode (11) of the thin film transistor, You may use for the transistor which comprises the data line drive circuit 34 which sends a signal to the data wiring 33 connected with a source electrode and a drain electrode.
  • the thin film transistor of each element and the thin film transistor in the gate line driving circuit 32 or the data line driving circuit 34 can be formed in parallel.
  • each element has a configuration as shown in FIG. 20, for example.
  • a scanning signal is supplied to the gate wiring 31 extending in the x direction in the figure, the thin film transistor 35 is turned on, and the image from the data wiring 33 extending in the y direction in the figure through the turned on thin film transistor 35.
  • a signal is supplied to the pixel electrode 36.
  • the gate lines 31 are arranged in parallel in the y direction in the figure, and the data lines 33 are arranged in parallel in the x direction in the figure and are surrounded by a pair of adjacent gate lines 31 and a pair of adjacent data lines 33.
  • a pixel electrode 36 is arranged in the area (pixel area).
  • the data line 33 is electrically connected to the source electrode
  • the pixel electrode 36 is electrically connected to the drain electrode.
  • the data wiring 33 may also serve as the source electrode.
  • the above-described array may be applied not only to the liquid crystal display device but also to an organic EL display device or the like. In this case, a thin film transistor is applied to a transistor included in the pixel circuit. Furthermore, the above-described array may be applied to the memory element, and a thin film transistor may be applied to the selection transistor.
  • the present invention can be applied to a semiconductor device having a thin film transistor using an oxide semiconductor material for a channel layer.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

L'invention vise à réduire la résistance de contact entre une couche d'oxyde semi-conducteur et une électrode de source/drain dans un transistor à couche mince qui utilise un matériau d'oxyde semi-conducteur comme couche de canal. Un transistor à couche mince, dans lequel une électrode de gâchette (11), une pellicule d'isolation de gâchette (12), une couche d'oxyde semi-conducteur amorphe (13) qui constitue une couche de canal, une électrode de source (14s) et une électrode de drain (14d) sont séquentiellement stratifiées dans cet ordre, est formé sur la surface supérieure d'un substrat (10). Des grains de cristal (13cg), qui contiennent un élément constituant de la couche d'oxyde semi-conducteur amorphe (13), sont formés dans la couche d'oxyde semi-conducteur amorphe (13) dans le voisinage de l'interface avec l'électrode de source (14s) et l'électrode de drain (14d). Les grains de cristal (13cg) sont formés en utilisant l'énergie de particules accélérées qui sont incidentes sur la couche d'oxyde semi-conducteur amorphe (13) quand une pellicule conductrice qui constitue l'électrode de source (14s) et l'électrode de drain (14d) est déposée.
PCT/JP2011/073879 2010-10-25 2011-10-18 Dispositif à oxyde semi-conducteur et son procédé de fabrication WO2012056933A1 (fr)

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Cited By (2)

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JP2012178439A (ja) * 2011-02-25 2012-09-13 Nippon Hoso Kyokai <Nhk> 半導体デバイス及びその製造方法
JP2018078339A (ja) * 2012-11-30 2018-05-17 株式会社半導体エネルギー研究所 半導体装置

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CN111710609A (zh) * 2020-06-24 2020-09-25 中国科学院微电子研究所 铟镓锌氧薄膜晶体管的掺杂方法

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JP5213421B2 (ja) * 2007-12-04 2013-06-19 キヤノン株式会社 酸化物半導体薄膜トランジスタ
JP2010153802A (ja) * 2008-11-20 2010-07-08 Semiconductor Energy Lab Co Ltd 半導体装置及び半導体装置の作製方法
JP5509659B2 (ja) * 2008-11-21 2014-06-04 凸版印刷株式会社 薄膜トランジスタ及びその製造方法並びに画像表示装置
JP5538797B2 (ja) * 2008-12-12 2014-07-02 キヤノン株式会社 電界効果型トランジスタ及び表示装置
KR20120107079A (ko) * 2009-11-20 2012-09-28 가부시키가이샤 한도오따이 에네루기 켄큐쇼 박막 트랜지스터
JP5657878B2 (ja) * 2009-11-20 2015-01-21 株式会社半導体エネルギー研究所 トランジスタの作製方法

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JP2010153828A (ja) * 2008-11-21 2010-07-08 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012178439A (ja) * 2011-02-25 2012-09-13 Nippon Hoso Kyokai <Nhk> 半導体デバイス及びその製造方法
JP2018078339A (ja) * 2012-11-30 2018-05-17 株式会社半導体エネルギー研究所 半導体装置

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