JP5602584B2 - 配線基板及びその製造方法 - Google Patents

配線基板及びその製造方法 Download PDF

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Publication number
JP5602584B2
JP5602584B2 JP2010241744A JP2010241744A JP5602584B2 JP 5602584 B2 JP5602584 B2 JP 5602584B2 JP 2010241744 A JP2010241744 A JP 2010241744A JP 2010241744 A JP2010241744 A JP 2010241744A JP 5602584 B2 JP5602584 B2 JP 5602584B2
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JP
Japan
Prior art keywords
layer
wiring
via hole
nickel
insulating resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2010241744A
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English (en)
Japanese (ja)
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JP2012094734A5 (enExample
JP2012094734A (ja
Inventor
隆司 伊藤
智生 山崎
勇太 坂口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2010241744A priority Critical patent/JP5602584B2/ja
Priority to US13/279,501 priority patent/US8878077B2/en
Publication of JP2012094734A publication Critical patent/JP2012094734A/ja
Publication of JP2012094734A5 publication Critical patent/JP2012094734A5/ja
Application granted granted Critical
Publication of JP5602584B2 publication Critical patent/JP5602584B2/ja
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2010241744A 2010-10-28 2010-10-28 配線基板及びその製造方法 Active JP5602584B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2010241744A JP5602584B2 (ja) 2010-10-28 2010-10-28 配線基板及びその製造方法
US13/279,501 US8878077B2 (en) 2010-10-28 2011-10-24 Wiring substrate and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010241744A JP5602584B2 (ja) 2010-10-28 2010-10-28 配線基板及びその製造方法

Publications (3)

Publication Number Publication Date
JP2012094734A JP2012094734A (ja) 2012-05-17
JP2012094734A5 JP2012094734A5 (enExample) 2013-08-15
JP5602584B2 true JP5602584B2 (ja) 2014-10-08

Family

ID=45995399

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010241744A Active JP5602584B2 (ja) 2010-10-28 2010-10-28 配線基板及びその製造方法

Country Status (2)

Country Link
US (1) US8878077B2 (enExample)
JP (1) JP5602584B2 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10849226B2 (en) 2018-12-04 2020-11-24 Samsung Electro-Mechanics Co., Ltd. Printed circuit board and method of manufacturing the same

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130118794A1 (en) * 2011-11-15 2013-05-16 Bo-Yu Tseng Package Substrate Structure
US20130168132A1 (en) * 2011-12-29 2013-07-04 Sumsung Electro-Mechanics Co., Ltd. Printed circuit board and method of manufacturing the same
CN103794544B (zh) * 2012-10-26 2016-04-13 中国科学院上海微系统与信息技术研究所 一种电镀铜的方法
US10028394B2 (en) * 2012-12-17 2018-07-17 Intel Corporation Electrical interconnect formed through buildup process
KR20140085023A (ko) * 2012-12-27 2014-07-07 삼성전기주식회사 인쇄 회로 기판 및 그 제조 방법
US9545003B2 (en) * 2012-12-28 2017-01-10 Fci Americas Technology Llc Connector footprints in printed circuit board (PCB)
KR101506785B1 (ko) * 2013-05-29 2015-03-27 삼성전기주식회사 인쇄회로기판
JP6266907B2 (ja) * 2013-07-03 2018-01-24 新光電気工業株式会社 配線基板及び配線基板の製造方法
CN105140198B (zh) * 2014-05-29 2017-11-28 日月光半导体制造股份有限公司 半导体衬底、半导体封装结构及其制造方法
JP6324876B2 (ja) * 2014-07-16 2018-05-16 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
CN105657988B (zh) * 2014-11-21 2019-04-23 宏启胜精密电子(秦皇岛)有限公司 柔性电路板及其制作方法
JP2016213283A (ja) * 2015-05-01 2016-12-15 ソニー株式会社 製造方法、および貫通電極付配線基板
EP3386282A4 (en) * 2015-11-30 2019-07-17 Toppan Printing Co., Ltd. MULTILAYER FITTED PCB AND METHOD FOR THE MANUFACTURE THEREOF
US10440836B2 (en) * 2016-04-26 2019-10-08 Kinsus Interconnect Technology Corp. Double layer circuit board
US20190174632A1 (en) * 2017-12-05 2019-06-06 Canon Components, Inc. Flexible printed circuit and electronic device
KR102680005B1 (ko) * 2018-11-27 2024-07-02 삼성전기주식회사 인쇄회로기판
KR20200087479A (ko) * 2019-01-11 2020-07-21 스템코 주식회사 다층 기판 및 그 제조 방법
CN113994770B (zh) 2019-05-31 2024-09-10 凸版印刷株式会社 多层配线基板及其制造方法
KR102827872B1 (ko) * 2020-07-30 2025-07-01 삼성전자주식회사 반도체 패키지
US12027467B2 (en) * 2021-01-29 2024-07-02 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
EP4319510A4 (en) * 2021-03-22 2024-10-02 Panasonic Intellectual Property Management Co., Ltd. WIRING BODY, MOUNTING SUBSTRATE, WIRING TRANSFER BOARD WITH WIRING, INTERMEDIATE MATERIAL FOR WIRING BODY, AND METHOD FOR MANUFACTURING WIRING BODY
US12414231B2 (en) * 2022-03-29 2025-09-09 Ibiden Co., Ltd. Printed wiring board
JP2023172732A (ja) * 2022-05-24 2023-12-06 イビデン株式会社 配線基板
JP7883388B2 (ja) * 2022-05-25 2026-07-01 イビデン株式会社 プリント配線板の製造方法
US20240237232A1 (en) * 2023-01-09 2024-07-11 Hannstar Display Corporation Circuit board and manufacturing method thereof, and light emitting module
JP2024112545A (ja) * 2023-02-08 2024-08-21 新光電気工業株式会社 配線基板及びその製造方法

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4969979A (en) * 1989-05-08 1990-11-13 International Business Machines Corporation Direct electroplating of through holes
JP3395621B2 (ja) * 1997-02-03 2003-04-14 イビデン株式会社 プリント配線板及びその製造方法
JPH1187931A (ja) 1997-09-11 1999-03-30 Ngk Spark Plug Co Ltd プリント配線板の製造方法
CN101094565A (zh) * 1997-12-11 2007-12-26 伊比登株式会社 多层印刷电路板的制造方法
JP2000022337A (ja) * 1998-06-30 2000-01-21 Matsushita Electric Works Ltd 多層配線板及びその製造方法
KR100855529B1 (ko) * 1998-09-03 2008-09-01 이비덴 가부시키가이샤 다층프린트배선판 및 그 제조방법
MY128333A (en) * 1998-09-14 2007-01-31 Ibiden Co Ltd Printed wiring board and its manufacturing method
JP4905749B2 (ja) 2001-03-02 2012-03-28 日立化成工業株式会社 配線板とその製造方法とその配線板を用いた半導体搭載用基板とその製造方法と半導体パッケージ並びにその製造方法
US7140103B2 (en) * 2001-06-29 2006-11-28 Mitsubishi Gas Chemical Company, Inc. Process for the production of high-density printed wiring board
JP4160765B2 (ja) * 2002-03-25 2008-10-08 京セラ株式会社 配線基板の製造方法
JP4094965B2 (ja) * 2003-01-28 2008-06-04 富士通株式会社 配線基板におけるビア形成方法
TWI262041B (en) * 2003-11-14 2006-09-11 Hitachi Chemical Co Ltd Formation method of metal layer on resin layer, printed wiring board, and production method thereof
WO2008053833A1 (fr) * 2006-11-03 2008-05-08 Ibiden Co., Ltd. Tableau de câblage imprimé multicouche
JP4303282B2 (ja) * 2006-12-22 2009-07-29 Ｔｄｋ株式会社 プリント配線板の配線構造及びその形成方法
JP4331769B2 (ja) * 2007-02-28 2009-09-16 Ｔｄｋ株式会社 配線構造及びその形成方法並びにプリント配線板
KR100905566B1 (ko) * 2007-04-30 2009-07-02 삼성전기주식회사 회로 전사용 캐리어 부재, 이를 이용한 코어리스인쇄회로기판, 및 이들의 제조방법
JP2009188324A (ja) * 2008-02-08 2009-08-20 Shinko Electric Ind Co Ltd 配線基板及びその製造方法
CN102265712B (zh) * 2008-12-26 2014-10-29 吉坤日矿日石金属株式会社 电子电路的形成方法
US20100270646A1 (en) * 2009-04-28 2010-10-28 Georgia Tech Research Corporation Thin-film capacitor structures embedded in semiconductor packages and methods of making
TWI393516B (zh) * 2009-06-01 2013-04-11 Unimicron Technology Crop 印刷電路板的製造方法
WO2010150310A1 (ja) * 2009-06-24 2010-12-29 富士通株式会社 配線基板の製造方法
JP5428667B2 (ja) * 2009-09-07 2014-02-26 日立化成株式会社 半導体チップ搭載用基板の製造方法
JP5436995B2 (ja) * 2009-09-14 2014-03-05 新光電気工業株式会社 配線基板及びその製造方法
US20110114372A1 (en) * 2009-10-30 2011-05-19 Ibiden Co., Ltd. Printed wiring board
US8334202B2 (en) * 2009-11-03 2012-12-18 Infineon Technologies Ag Device fabricated using an electroplating process
JP4546581B2 (ja) * 2010-05-12 2010-09-15 新光電気工業株式会社 配線基板の製造方法
JP2012216773A (ja) * 2011-03-29 2012-11-08 Shinko Electric Ind Co Ltd 配線基板及びその製造方法
US20120247818A1 (en) * 2011-03-29 2012-10-04 Ibiden Co., Ltd. Printed wiring board
JP5833398B2 (ja) * 2011-06-27 2015-12-16 新光電気工業株式会社 配線基板及びその製造方法、半導体装置
US20130118794A1 (en) * 2011-11-15 2013-05-16 Bo-Yu Tseng Package Substrate Structure
KR102069158B1 (ko) * 2012-05-10 2020-01-22 가부시키가이샤 한도오따이 에네루기 켄큐쇼 배선의 형성 방법, 반도체 장치, 및 반도체 장치의 제작 방법

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10849226B2 (en) 2018-12-04 2020-11-24 Samsung Electro-Mechanics Co., Ltd. Printed circuit board and method of manufacturing the same

Also Published As

Publication number Publication date
US20120103667A1 (en) 2012-05-03
US8878077B2 (en) 2014-11-04
JP2012094734A (ja) 2012-05-17

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