JP5598677B2 - メモリの動作条件に作用するためのパラメータを含むメモリ命令 - Google Patents
メモリの動作条件に作用するためのパラメータを含むメモリ命令 Download PDFInfo
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- JP5598677B2 JP5598677B2 JP2011235151A JP2011235151A JP5598677B2 JP 5598677 B2 JP5598677 B2 JP 5598677B2 JP 2011235151 A JP2011235151 A JP 2011235151A JP 2011235151 A JP2011235151 A JP 2011235151A JP 5598677 B2 JP5598677 B2 JP 5598677B2
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/60—Protecting data
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
- G11C14/0054—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell
- G11C14/0063—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
- G11C14/0054—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell
- G11C14/009—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/107—Programming all cells in an array, sector or block to the same state prior to flash erasing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/12—Programming voltage switching circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/109—Control signal input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7204—Capacity control, e.g. partitioning, end-of-life degradation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5671—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge trapping in an insulator
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Theoretical Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Software Systems (AREA)
- Health & Medical Sciences (AREA)
- Computer Hardware Design (AREA)
- General Health & Medical Sciences (AREA)
- Bioethics (AREA)
- Read Only Memory (AREA)
- Memory System (AREA)
Description
ここに説明する実施形態は一つ以上の動作パラメータ(例えば入力情報からなる動作パラメータ)からなっているが、動作パラメータはまたコマンドの実行結果である情報(例えば出力情報からなる動作パラメータ)からなってもよい。そのような一つ以上の動作パラメータはまた、コマンドの実行結果を伴ってもよい。例えば、一つ以上の動作パラメータは、読出しコマンドの実行から結果として生じる読出しデータを伴ってもよい。或る実装においては、動作パラメータは、或る動作が実行されたときの読出し電圧を表してもよい。
Claims (11)
- メモリ内の位置で動作するコマンドおよび少なくとも一つの動作パラメータを含むメモリ命令を受信することと、
前記メモリ内の前記位置で動作する前記コマンドの実行中に、前記少なくとも一つの動作パラメータに少なくとも部分的に基づいて周辺回路の物理的な動作条件に作用すること であって、前記物理的な動作条件は、前記メモリの精度および前記メモリの動作速度のう ちの少なくとも一つを含む、ことと、
を含むことを特徴とする方法。 - 請求項1に記載の方法であって、前記少なくとも一つの動作パラメータは、デジタル信号を含む、ことを特徴とする方法。
- 請求項2に記載の方法であって、前記デジタル信号をアナログ信号に変換することをさらに含む、ことを特徴とする方法。
- 請求項2に記載の方法であって、
前記デジタル信号に対応する電圧または電流を生成することと、
前記電圧または電流を前記メモリに含まれる一つ以上の周辺回路に印加することと、
をさらに含む、ことを特徴とする方法。 - 請求項1に記載の方法であって、前記コマンドは、前記メモリから読み出し、前記メモリに書き込み、または前記メモリの少なくとも一部を消去するためのコマンドを含む、ことを特徴とする方法。
- 請求項1に記載の方法であって、
前記メモリ命令とともに含まれる追加の動作パラメータを受信することをさらに含み、
前記追加の動作パラメータは、前記少なくとも一つの動作パラメータが、引き続く命令の間中に適用されるのか否かを示す、ことを特徴とする方法。 - メモリデバイスであって、
メモリセルのアレイからの読み出しまたはメモリセルのアレイへの書き込みを行い、かつ、前記メモリセルのアレイ内の位置で動作するコマンドおよび少なくとも一つの動作パラメータを含むメモリ命令を受信する、ための回路と、
前記少なくとも一つの動作パラメータを受信し、かつ、前記メモリセルのアレイ内の前 記位置で動作する前記コマンドの実行中に、前記少なくとも一つの動作パラメータに少なくとも部分的に基づいて前記回路の物理的な動作条件に作用する、ためのパラメータ管理ブロックであって、前記物理的な動作条件は、前記メモリデバイスの精度および前記メモ リデバイスの動作速度のうちの少なくとも一つを含む、パラメータ管理ブロックと、
を備えることを特徴とするメモリデバイス。 - 請求項7に記載のメモリデバイスであって、前記少なくとも一つの動作パラメータに少なくとも一部が基づいて電圧または電流のレベルを生成するジェネレータをさらに備える、ことを特徴とするメモリデバイス。
- 請求項7に記載のメモリデバイスであって、
前記少なくとも一つの動作パラメータを受信するための第1の入力ポートと、
前記コマンドを受信するための第2の入力ポートと、
をさらに備えることを特徴とするメモリデバイス。 - 請求項7に記載のメモリデバイスであって、前記回路はさらに、前記メモリセルのアレイ内の前記位置を表すアドレスを受信する、ことを特徴とするメモリデバイス。
- メモリセルのアレイを備えたメモリデバイスと、プロセッサと、を備えるシステムであって、
前記メモリデバイスはメモリコントローラをさらに備え、前記メモリコントローラは、前記メモリセルのアレイからの読み出しまたは前記メモリセルのアレイ への書き込みを行い、前記メモリセルのアレイ内の位置で動作するコマンドおよび少なくとも一つの動作パラメータを含むメモリ命令を受信し、かつ、前記メモリセルのアレイ内の前記位置で動 作する前記コマンドの実行中に、前記少なくとも一つの動作パラメータに少なくとも部分 的に基づいて前記メモリデバイス内の周辺回路の物理的な動作条件に作用し、前記物理的 な動作条件は、前記メモリデバイスの精度および前記メモリデバイスの動作速度のうちの 少なくとも一つを含み、
前記プロセッサは、一つ以上のアプリケーションを提供し、かつ、前記メモリコントローラへの前記メモリ命令を創始して前記メモリセルのアレイへのアクセスを提供する、ことを特徴とするシステム。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US12/949,728 | 2010-11-18 | ||
US12/949,728 US8737138B2 (en) | 2010-11-18 | 2010-11-18 | Memory instruction including parameter to affect operating condition of memory |
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JP2012109003A JP2012109003A (ja) | 2012-06-07 |
JP5598677B2 true JP5598677B2 (ja) | 2014-10-01 |
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JP2011235151A Active JP5598677B2 (ja) | 2010-11-18 | 2011-10-26 | メモリの動作条件に作用するためのパラメータを含むメモリ命令 |
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US (4) | US8737138B2 (ja) |
JP (1) | JP5598677B2 (ja) |
KR (2) | KR101430295B1 (ja) |
CN (1) | CN102543154B (ja) |
DE (1) | DE102011085988B4 (ja) |
TW (1) | TWI508093B (ja) |
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US20130167251A1 (en) | 2013-06-27 |
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US20140250280A1 (en) | 2014-09-04 |
US8824213B2 (en) | 2014-09-02 |
TW201227750A (en) | 2012-07-01 |
KR20140066988A (ko) | 2014-06-03 |
DE102011085988B4 (de) | 2018-01-11 |
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