JP5459987B2 - 半導体基板及び半導体基板の作製方法、半導体装置、電子機器 - Google Patents

半導体基板及び半導体基板の作製方法、半導体装置、電子機器 Download PDF

Info

Publication number
JP5459987B2
JP5459987B2 JP2008166433A JP2008166433A JP5459987B2 JP 5459987 B2 JP5459987 B2 JP 5459987B2 JP 2008166433 A JP2008166433 A JP 2008166433A JP 2008166433 A JP2008166433 A JP 2008166433A JP 5459987 B2 JP5459987 B2 JP 5459987B2
Authority
JP
Japan
Prior art keywords
single crystal
crystal semiconductor
layer
substrate
insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2008166433A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009033135A (ja
JP2009033135A5 (enExample
Inventor
智史 村上
宏充 郷戸
敦生 磯部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP2008166433A priority Critical patent/JP5459987B2/ja
Publication of JP2009033135A publication Critical patent/JP2009033135A/ja
Publication of JP2009033135A5 publication Critical patent/JP2009033135A5/ja
Application granted granted Critical
Publication of JP5459987B2 publication Critical patent/JP5459987B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0214—Manufacture or treatment of multiple TFTs using temporary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P34/00—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices
    • H10P34/40—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices with high-energy radiation
    • H10P34/42—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices with high-energy radiation with electromagnetic radiation, e.g. laser annealing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P36/00—Gettering within semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
    • H10P14/3802—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H10P14/3808—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams

Landscapes

  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)
JP2008166433A 2007-06-26 2008-06-25 半導体基板及び半導体基板の作製方法、半導体装置、電子機器 Expired - Fee Related JP5459987B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008166433A JP5459987B2 (ja) 2007-06-26 2008-06-25 半導体基板及び半導体基板の作製方法、半導体装置、電子機器

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2007167356 2007-06-26
JP2007167356 2007-06-26
JP2008166433A JP5459987B2 (ja) 2007-06-26 2008-06-25 半導体基板及び半導体基板の作製方法、半導体装置、電子機器

Publications (3)

Publication Number Publication Date
JP2009033135A JP2009033135A (ja) 2009-02-12
JP2009033135A5 JP2009033135A5 (enExample) 2011-06-23
JP5459987B2 true JP5459987B2 (ja) 2014-04-02

Family

ID=40161087

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008166433A Expired - Fee Related JP5459987B2 (ja) 2007-06-26 2008-06-25 半導体基板及び半導体基板の作製方法、半導体装置、電子機器

Country Status (3)

Country Link
US (1) US7867873B2 (enExample)
JP (1) JP5459987B2 (enExample)
KR (1) KR101484296B1 (enExample)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10260149A1 (de) * 2002-12-20 2004-07-01 BSH Bosch und Siemens Hausgeräte GmbH Vorrichtung zur Bestimmung des Leitwertes von Wäsche, Wäschetrockner und Verfahren zur Verhinderung von Schichtbildung auf Elektroden
CN101281912B (zh) * 2007-04-03 2013-01-23 株式会社半导体能源研究所 Soi衬底及其制造方法以及半导体装置
JP5527956B2 (ja) * 2007-10-10 2014-06-25 株式会社半導体エネルギー研究所 半導体基板の製造方法
JP5490393B2 (ja) * 2007-10-10 2014-05-14 株式会社半導体エネルギー研究所 半導体基板の製造方法
JP5503876B2 (ja) * 2008-01-24 2014-05-28 株式会社半導体エネルギー研究所 半導体基板の製造方法
JP5548395B2 (ja) * 2008-06-25 2014-07-16 株式会社半導体エネルギー研究所 Soi基板の作製方法
US8741740B2 (en) * 2008-10-02 2014-06-03 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
JP2010114431A (ja) * 2008-10-10 2010-05-20 Semiconductor Energy Lab Co Ltd Soi基板の作製方法
JP5338396B2 (ja) * 2009-03-12 2013-11-13 パナソニック株式会社 弾性表面波デバイスの製造方法
KR20120059509A (ko) * 2009-08-25 2012-06-08 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 그 제작 방법
US8324084B2 (en) * 2010-03-31 2012-12-04 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of semiconductor substrate and manufacturing method of semiconductor device
JP5917036B2 (ja) 2010-08-05 2016-05-11 株式会社半導体エネルギー研究所 Soi基板の作製方法
TWI500118B (zh) 2010-11-12 2015-09-11 半導體能源研究所股份有限公司 半導體基底之製造方法
JP2012156495A (ja) 2011-01-07 2012-08-16 Semiconductor Energy Lab Co Ltd Soi基板の作製方法
US8802534B2 (en) 2011-06-14 2014-08-12 Semiconductor Energy Laboratory Co., Ltd. Method for forming SOI substrate and apparatus for forming the same
US8735219B2 (en) 2012-08-30 2014-05-27 Ziptronix, Inc. Heterogeneous annealing method and device
JP5859497B2 (ja) * 2013-08-22 2016-02-10 信越化学工業株式会社 界面近傍における欠陥密度が低いsos基板の製造方法
JP5859496B2 (ja) * 2013-08-22 2016-02-10 信越化学工業株式会社 表面欠陥密度が少ないsos基板の製造方法
JP6396852B2 (ja) * 2015-06-02 2018-09-26 信越化学工業株式会社 酸化物単結晶薄膜を備えた複合ウェーハの製造方法
JP6396853B2 (ja) 2015-06-02 2018-09-26 信越化学工業株式会社 酸化物単結晶薄膜を備えた複合ウェーハの製造方法
JP6454606B2 (ja) 2015-06-02 2019-01-16 信越化学工業株式会社 酸化物単結晶薄膜を備えた複合ウェーハの製造方法
US11664357B2 (en) 2018-07-03 2023-05-30 Adeia Semiconductor Bonding Technologies Inc. Techniques for joining dissimilar materials in microelectronics
CN114761174A (zh) * 2019-11-25 2022-07-15 康宁股份有限公司 粘结制品及其形成方法
US11081393B2 (en) * 2019-12-09 2021-08-03 Infineon Technologies Ag Method for splitting semiconductor wafers
KR20260077969A (ko) 2020-03-19 2026-05-28 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 직접 결합된 구조체들을 위한 치수 보상 제어
CN113541626B (zh) * 2020-04-21 2025-07-22 济南晶正电子科技有限公司 一种复合单晶压电基板及制备方法
CN111477543A (zh) * 2020-04-23 2020-07-31 济南晶正电子科技有限公司 一种键合衬底晶圆与单晶压电晶圆的方法及复合单晶压电晶圆基板
DE102021110742B4 (de) 2021-04-27 2025-01-16 Infineon Technologies Ag Verfahren zum teilen von halbleiterwerkstücken, halbleiterwerkstück und gerät zum definieren eines trennbereichs in halbleiterwerkstücken
US12136691B2 (en) * 2022-01-18 2024-11-05 Apple Inc. System with one-way filter over light-emitting elements

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0834198B2 (ja) * 1990-11-28 1996-03-29 信越半導体株式会社 Soi基板における単結晶薄膜層の膜厚制御方法
FR2681472B1 (fr) 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
JPH05335530A (ja) * 1992-05-28 1993-12-17 Sony Corp Soi基板の製造方法
US6534380B1 (en) * 1997-07-18 2003-03-18 Denso Corporation Semiconductor substrate and method of manufacturing the same
US6014944A (en) * 1997-09-19 2000-01-18 The United States Of America As Represented By The Secretary Of The Navy Apparatus for improving crystalline thin films with a contoured beam pulsed laser
JPH11163363A (ja) 1997-11-22 1999-06-18 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
JP2000012864A (ja) 1998-06-22 2000-01-14 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
US6271101B1 (en) 1998-07-29 2001-08-07 Semiconductor Energy Laboratory Co., Ltd. Process for production of SOI substrate and process for production of semiconductor device
JP4476390B2 (ja) 1998-09-04 2010-06-09 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP2000124092A (ja) 1998-10-16 2000-04-28 Shin Etsu Handotai Co Ltd 水素イオン注入剥離法によってsoiウエーハを製造する方法およびこの方法で製造されたsoiウエーハ
JP4379943B2 (ja) 1999-04-07 2009-12-09 株式会社デンソー 半導体基板の製造方法および半導体基板製造装置
TW487959B (en) * 1999-08-13 2002-05-21 Semiconductor Energy Lab Laser apparatus, laser annealing method, and manufacturing method of a semiconductor device
US6548370B1 (en) 1999-08-18 2003-04-15 Semiconductor Energy Laboratory Co., Ltd. Method of crystallizing a semiconductor layer by applying laser irradiation that vary in energy to its top and bottom surfaces
JP4919530B2 (ja) 1999-08-18 2012-04-18 株式会社半導体エネルギー研究所 半導体装置の作製方法
US20010053559A1 (en) * 2000-01-25 2001-12-20 Semiconductor Energy Laboratory Co., Ltd. Method of fabricating display device
JP4507395B2 (ja) * 2000-11-30 2010-07-21 セイコーエプソン株式会社 電気光学装置用素子基板の製造方法
TW544938B (en) 2001-06-01 2003-08-01 Semiconductor Energy Lab Method of manufacturing a semiconductor device
EP1455394B1 (en) * 2001-07-24 2018-04-11 Samsung Electronics Co., Ltd. Transfer method
US7119365B2 (en) 2002-03-26 2006-10-10 Sharp Kabushiki Kaisha Semiconductor device and manufacturing method thereof, SOI substrate and display device using the same, and manufacturing method of the SOI substrate
US7050387B2 (en) * 2002-06-28 2006-05-23 Victor Company Of Japan, Ltd. Optical storage medium
JP4328067B2 (ja) * 2002-07-31 2009-09-09 アプライド マテリアルズ インコーポレイテッド イオン注入方法及びsoiウエハの製造方法、並びにイオン注入装置
FR2847075B1 (fr) 2002-11-07 2005-02-18 Commissariat Energie Atomique Procede de formation d'une zone fragile dans un substrat par co-implantation
JP4759919B2 (ja) 2004-01-16 2011-08-31 セイコーエプソン株式会社 電気光学装置の製造方法
JP5110772B2 (ja) 2004-02-03 2012-12-26 株式会社半導体エネルギー研究所 半導体薄膜層を有する基板の製造方法
US7410882B2 (en) * 2004-09-28 2008-08-12 Palo Alto Research Center Incorporated Method of manufacturing and structure of polycrystalline semiconductor thin-film heterostructures on dissimilar substrates
US7148124B1 (en) * 2004-11-18 2006-12-12 Alexander Yuri Usenko Method for forming a fragile layer inside of a single crystalline substrate preferably for making silicon-on-insulator wafers
US20070281440A1 (en) * 2006-05-31 2007-12-06 Jeffrey Scott Cites Producing SOI structure using ion shower
KR101440930B1 (ko) 2007-04-20 2014-09-15 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Soi 기판의 제작방법

Also Published As

Publication number Publication date
KR101484296B1 (ko) 2015-01-19
KR20080114512A (ko) 2008-12-31
US20090004822A1 (en) 2009-01-01
US7867873B2 (en) 2011-01-11
JP2009033135A (ja) 2009-02-12

Similar Documents

Publication Publication Date Title
JP2009033135A (ja) 半導体基板及び半導体基板の作製方法、半導体装置、電子機器
US7763502B2 (en) Semiconductor substrate, method for manufacturing semiconductor substrate, semiconductor device, and electronic device
US8368082B2 (en) Method for manufacturing semiconductor device, semiconductor device and electronic appliance
US7947570B2 (en) Manufacturing method and manufacturing apparatus of semiconductor substrate
US7851332B2 (en) Semiconductor device and method for manufacturing the same
US8470688B2 (en) Semiconductor device and method for manufacturing the same
US8309429B2 (en) Method for manufacturing semiconductor substrate and semiconductor device
US7816232B2 (en) Method for manufacturing semiconductor substrate and semiconductor substrate manufacturing apparatus
US7816234B2 (en) Method for manufacturing semiconductor device
JP5322520B2 (ja) 半導体装置、電子機器、及び半導体装置の作製方法
JP5188355B2 (ja) 半導体装置の作製方法、半導体装置
JP2011009723A (ja) Soi基板の作製方法
US8236630B2 (en) Manufacturing method of semiconductor device, semiconductor device, and electronic device

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110511

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20110511

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130529

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20130530

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130614

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20140107

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20140114

R150 Certificate of patent or registration of utility model

Ref document number: 5459987

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees