JP5188355B2 - 半導体装置の作製方法、半導体装置 - Google Patents
半導体装置の作製方法、半導体装置 Download PDFInfo
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- JP5188355B2 JP5188355B2 JP2008267510A JP2008267510A JP5188355B2 JP 5188355 B2 JP5188355 B2 JP 5188355B2 JP 2008267510 A JP2008267510 A JP 2008267510A JP 2008267510 A JP2008267510 A JP 2008267510A JP 5188355 B2 JP5188355 B2 JP 5188355B2
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- insulating layer
- layer
- insulator
- fluorine
- semiconductor device
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Images
Classifications
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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- H01L21/31629—Deposition of halogen doped silicon oxide, e.g. fluorine doped silicon oxide
Description
本実施の形態では、開示発明に係る絶縁層について、図1乃至6を参照して説明する。
本実施の形態では、開示発明の絶縁層を用いた半導体装置の一例について、図7乃至11を参照して説明する。
本実施の形態では、開示発明に係る絶縁層を用いた半導体装置の一例として、液晶表示装置の製造方法の一例について図12乃至15を参照して説明する。
本実施の形態では、開示発明に係る発光素子を有する半導体装置(エレクトロルミネッセンス表示装置)について説明する。なお、周辺回路領域や画素領域等に用いられるトランジスタの作製方法は、実施の形態3等を参照することができるため、詳細については省略する。
本実施の形態では、開示発明に係る半導体装置の別の例について、図17及び18を参照して説明する。なお、本実施の形態においては、マイクロプロセッサ及び電子タグを例に挙げて説明するが、開示発明に係る半導体装置はこれらに限られるものではない。
本実施の形態では、開示発明に係る半導体装置、特に表示装置を用いた電子機器について、図19を参照して説明する。
本実施の形態では、開示発明に係る半導体装置、特に無線タグの使用例について、図20を参照して説明する。
102 絶縁体
104 絶縁体
106 絶縁層
200 プラズマCVD装置
202 下部電極
204 上部電極
206 ガス導入部
208 排気口
210 処理室
212 高周波電源
300 基板
302 酸化窒化珪素
304 窒化珪素
306 絶縁層
308 レジストマスク
310 構造
312 間隙
400 酸化窒化珪素
402 酸化窒化珪素
404 酸化窒化珪素
500 酸化窒化珪素
502 酸化窒化珪素
504 酸化窒化珪素
600 窒化珪素
700 単結晶半導体基板
702 脆化層
704 単結晶半導体層
706 絶縁層
710 基板
900 基板
902 絶縁層
904 単結晶半導体層
906 ゲート絶縁層
908 単結晶半導体層
910 単結晶半導体層
912 ゲート電極層
914 ゲート電極層
916 マスク
918 n型不純物領域
920 n型不純物領域
922 チャネル形成領域
924 マスク
926 p型不純物領域
928 p型不純物領域
930 チャネル形成領域
932 絶縁層
934 ドレイン電極層
936 ドレイン電極層
938 ドレイン電極層
940 nチャネル型トランジスタ
942 pチャネル型トランジスタ
1100 nチャネル型トランジスタ
1102 pチャネル型トランジスタ
1104 ゲート電極
1200 基板
1202 絶縁層
1204 絶縁層
1206 単結晶半導体層
1208 ゲート絶縁層
1210 単結晶半導体層
1212 単結晶半導体層
1214 単結晶半導体層
1216a マスク
1216b マスク
1216c マスク
1216d マスク
1216e マスク
1218a ゲート電極層
1218b ゲート電極層
1218c ゲート電極層
1218d ゲート電極層
1218e 導電層
1220a 導電層
1220b 導電層
1220c 導電層
1220d 導電層
1220e 導電層
1222a ゲート電極層
1222b ゲート電極層
1222c ゲート電極層
1222d ゲート電極層
1222e 導電層
1224a ゲート電極層
1224b ゲート電極層
1224c ゲート電極層
1224d ゲート電極層
1224e 導電層
1226a n型不純物領域
1226b n型不純物領域
1228a n型不純物領域
1228b n型不純物領域
1230a n型不純物領域
1230b n型不純物領域
1230c n型不純物領域
1232a マスク
1232b マスク
1232c マスク
1234a n型不純物領域
1234b n型不純物領域
1236a n型不純物領域
1236b n型不純物領域
1238 チャネル形成領域
1240a n型不純物領域
1240b n型不純物領域
1240c n型不純物領域
1242a n型不純物領域
1242b n型不純物領域
1242c n型不純物領域
1242d n型不純物領域
1244a チャネル形成領域
1244b チャネル形成領域
1246a マスク
1246b マスク
1248a p型不純物領域
1248b p型不純物領域
1250a p型不純物領域
1250b p型不純物領域
1252 チャネル形成領域
1254 絶縁層
1258a ドレイン電極層
1258b ドレイン電極層
1260a ドレイン電極層
1260b ドレイン電極層
1262a ドレイン電極層
1262b ドレイン電極層
1264 pチャネル型薄膜トランジスタ
1266 nチャネル型薄膜トランジスタ
1268 nチャネル型薄膜トランジスタ
1270 容量配線
1272 絶縁層
1274 画素電極層
1276 外部端子接続領域
1278 封止領域
1280 周辺駆動回路領域
1282 画素領域
1500 対向基板
1502 絶縁層
1504 液晶層
1506 絶縁層
1508 導電層
1510 着色層
1512 偏光子
1514 シール材
1516 スペーサ
1518 偏光子
1520 端子電極層
1522 異方性導電体層
1524 FPC
1600 基板
1602 絶縁膜
1630 外部端子接続領域
1632 封止領域
1634 駆動回路領域
1636 画素領域
1650 薄膜トランジスタ
1652 薄膜トランジスタ
1654 薄膜トランジスタ
1656 薄膜トランジスタ
1660 発光素子
1662 電極層
1664 発光層
1666 電極層
1668 絶縁層
1670 充填材
1672 シール材
1674 配線層
1676 端子電極層
1678 異方性導電層
1680 FPC
1690 封止基板
1700 マイクロプロセッサ
1701 演算回路
1702 演算回路制御部
1703 命令解析部
1704 制御部
1705 タイミング制御部
1706 レジスタ
1707 レジスタ制御部
1708 バスインターフェース
1709 ROM
1710 ROMインターフェース
1800 無線タグ
1801 アナログ回路部
1802 デジタル回路部
1803 共振回路
1804 整流回路
1805 定電圧回路
1806 リセット回路
1807 発振回路
1808 復調回路
1809 変調回路
1810 RFインターフェース
1811 制御レジスタ
1812 クロックコントローラ
1813 CPUインターフェース
1814 CPU
1815 RAM
1816 ROM
1817 アンテナ
1818 容量部
1819 電源管理回路
1901 筺体
1902 支持台
1903 表示部
1904 スピーカー部
1905 ビデオ入力端子
1911 本体
1912 表示部
1913 受像部
1914 操作キー
1915 外部接続ポート
1916 シャッターボタン
1921 本体
1922 筐体
1923 表示部
1924 キーボード
1925 外部接続ポート
1926 ポインティングデバイス
1931 本体
1932 表示部
1933 スイッチ
1934 操作キー
1935 赤外線ポート
1941 本体
1942 筐体
1943 表示部
1944 表示部
1945 記録媒体読み込み部
1946 操作キー
1947 スピーカー部
1951 本体
1952 表示部
1953 操作キー
1961 本体
1962 表示部
1963 筐体
1964 外部接続ポート
1965 リモコン受信部
1966 受像部
1967 バッテリー
1968 音声入力部
1969 操作キー
1971 本体
1972 筐体
1973 表示部
1974 音声入力部
1975 音声出力部
1976 操作キー
1977 外部接続ポート
1978 アンテナ
S2100 ステップ
S2102 ステップ
S2104 ステップ
S2106 ステップ
Claims (11)
- 基板上に半導体層を有する半導体装置の作製方法であって、
窒素を含有する第1の絶縁体の堆積と、窒素及びフッ素を含有する第2の絶縁体の堆積を複数回繰り返すことにより、前記半導体層上に、窒素を含有する第1の領域と、窒素及びフッ素を含有する第2の領域を交互に有する絶縁層を形成し、
前記第1の絶縁体の堆積は、窒素及び珪素を含有するガスを原料ガスとして用いたプラズマCVD法により行われ、
前記第2の絶縁体の堆積は、前記第1の絶縁体の堆積に用いられる原料ガスにフッ素を添加したガスを原料ガスとして用いたプラズマCVD法により行われ、
前記第1の絶縁体の堆積と、前記第2の絶縁体の堆積とは、同一装置内において連続的に行われることを特徴とする半導体装置の作製方法。 - 請求項1において、
前記第1の絶縁体は、酸化窒化珪素又は窒化酸化珪素であり、
前記第2の絶縁体は、フッ素を含有する酸化窒化珪素又はフッ素を含有する窒化酸化珪素であることを特徴とする半導体装置の作製方法。 - 請求項1又は2において、
前記絶縁層の最上面は前記第1の絶縁体により形成されることを特徴とする半導体装置の作製方法。 - 請求項1乃至3のいずれか一において、
前記第1の領域を、下部から上部に向かうにつれて厚くなるように形成することを特徴とする半導体装置の作製方法。 - 請求項1乃至4のいずれか一において、
前記第2の領域を、下部から上部に向かうにつれて薄くなるように形成することを特徴とする半導体装置の作製方法。 - 請求項1乃至5のいずれか一において、
前記第2の領域におけるフッ素の濃度を、5×1018atoms/cm3以上1×1021atoms/cm3以下とすることを特徴とする半導体装置の作製方法。 - 請求項1乃至6のいずれか一において、
前記絶縁層を、ドライエッチングを用いて加工することを特徴とする半導体装置の作製方法。 - 基板上の半導体層と、
前記半導体層上の絶縁層を有し、
前記絶縁層は、窒素を含有する第1の絶縁体からなる第1の領域と、窒素及びフッ素を含有する第2の絶縁体からなる第2の領域を交互に複数有し、
前記第1の絶縁体は、酸化窒化珪素又は窒化酸化珪素であり、
前記第2の絶縁体は、フッ素を含有する酸化窒化珪素又はフッ素を含有する窒化酸化珪素であり、
前記絶縁層の最上面は前記第1の絶縁体からなり、
前記第1の領域は、下部から上部に向かうにつれて厚くなるように形成されていることを特徴とする半導体装置。 - 請求項8において、
前記第2の領域は、下部から上部に向かうにつれて薄くなるように形成されていることを特徴とする半導体装置。 - 請求項8又は9において、
前記絶縁層の深さ方向の元素濃度のプロファイルにおいて、フッ素の濃度は前記第2の領域においてピークを有し、窒素の濃度は前記第2の領域においてピークを有しないことを特徴とする半導体装置。 - 請求項8乃至10のいずれか一において、
前記第2の領域におけるフッ素の濃度は、5×1018atoms/cm3以上1×1021atoms/cm3であることを特徴とする半導体装置。
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JP6494411B2 (ja) * | 2014-06-24 | 2019-04-03 | 東京エレクトロン株式会社 | 成膜方法および成膜装置 |
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US5661334A (en) * | 1996-01-16 | 1997-08-26 | Micron Technology, Inc. | Inter-metal dielectric structure which combines fluorine-doped glass and barrier layers |
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US6157083A (en) | 1996-06-03 | 2000-12-05 | Nec Corporation | Fluorine doping concentrations in a multi-structure semiconductor device |
US5935334A (en) * | 1996-11-13 | 1999-08-10 | Applied Materials, Inc. | Substrate processing apparatus with bottom-mounted remote plasma system |
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