KR101484296B1 - 반도체 기판의 제작방법 - Google Patents

반도체 기판의 제작방법 Download PDF

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Publication number
KR101484296B1
KR101484296B1 KR20080052126A KR20080052126A KR101484296B1 KR 101484296 B1 KR101484296 B1 KR 101484296B1 KR 20080052126 A KR20080052126 A KR 20080052126A KR 20080052126 A KR20080052126 A KR 20080052126A KR 101484296 B1 KR101484296 B1 KR 101484296B1
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Prior art keywords
single crystal
crystal semiconductor
substrate
insulating layer
semiconductor substrate
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Korean (ko)
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KR20080114512A (ko
Inventor
사토시 무라카미
히로미치 고도
아츠오 이소베
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가부시키가이샤 한도오따이 에네루기 켄큐쇼
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0214—Manufacture or treatment of multiple TFTs using temporary substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)
KR20080052126A 2007-06-26 2008-06-03 반도체 기판의 제작방법 Expired - Fee Related KR101484296B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007167356 2007-06-26
JPJP-P-2007-00167356 2007-06-26

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Publication Number Publication Date
KR20080114512A KR20080114512A (ko) 2008-12-31
KR101484296B1 true KR101484296B1 (ko) 2015-01-19

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US (1) US7867873B2 (enExample)
JP (1) JP5459987B2 (enExample)
KR (1) KR101484296B1 (enExample)

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CN101281912B (zh) 2007-04-03 2013-01-23 株式会社半导体能源研究所 Soi衬底及其制造方法以及半导体装置
JP5490393B2 (ja) * 2007-10-10 2014-05-14 株式会社半導体エネルギー研究所 半導体基板の製造方法
JP5527956B2 (ja) * 2007-10-10 2014-06-25 株式会社半導体エネルギー研究所 半導体基板の製造方法
JP5503876B2 (ja) * 2008-01-24 2014-05-28 株式会社半導体エネルギー研究所 半導体基板の製造方法
JP5548395B2 (ja) * 2008-06-25 2014-07-16 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
US8741740B2 (en) * 2008-10-02 2014-06-03 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
JP2010114431A (ja) * 2008-10-10 2010-05-20 Semiconductor Energy Lab Co Ltd Ｓｏｉ基板の作製方法
JP5338396B2 (ja) * 2009-03-12 2013-11-13 パナソニック株式会社 弾性表面波デバイスの製造方法
KR20120059509A (ko) * 2009-08-25 2012-06-08 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 그 제작 방법
US8324084B2 (en) * 2010-03-31 2012-12-04 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of semiconductor substrate and manufacturing method of semiconductor device
JP5917036B2 (ja) 2010-08-05 2016-05-11 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
TWI500118B (zh) 2010-11-12 2015-09-11 Semiconductor Energy Lab 半導體基底之製造方法
JP2012156495A (ja) 2011-01-07 2012-08-16 Semiconductor Energy Lab Co Ltd Ｓｏｉ基板の作製方法
US8802534B2 (en) 2011-06-14 2014-08-12 Semiconductor Energy Laboratory Co., Ltd. Method for forming SOI substrate and apparatus for forming the same
US8735219B2 (en) 2012-08-30 2014-05-27 Ziptronix, Inc. Heterogeneous annealing method and device
JP5859497B2 (ja) * 2013-08-22 2016-02-10 信越化学工業株式会社 界面近傍における欠陥密度が低いｓｏｓ基板の製造方法
JP5859496B2 (ja) * 2013-08-22 2016-02-10 信越化学工業株式会社 表面欠陥密度が少ないｓｏｓ基板の製造方法
JP6396852B2 (ja) * 2015-06-02 2018-09-26 信越化学工業株式会社 酸化物単結晶薄膜を備えた複合ウェーハの製造方法
JP6454606B2 (ja) 2015-06-02 2019-01-16 信越化学工業株式会社 酸化物単結晶薄膜を備えた複合ウェーハの製造方法
JP6396853B2 (ja) 2015-06-02 2018-09-26 信越化学工業株式会社 酸化物単結晶薄膜を備えた複合ウェーハの製造方法
US11664357B2 (en) 2018-07-03 2023-05-30 Adeia Semiconductor Bonding Technologies Inc. Techniques for joining dissimilar materials in microelectronics
KR20220107219A (ko) * 2019-11-25 2022-08-02 코닝 인코포레이티드 접합 물품 및 이를 형성하는 방법
US11081393B2 (en) * 2019-12-09 2021-08-03 Infineon Technologies Ag Method for splitting semiconductor wafers
WO2021188846A1 (en) 2020-03-19 2021-09-23 Invensas Bonding Technologies, Inc. Dimension compensation control for directly bonded structures
CN113541626B (zh) * 2020-04-21 2025-07-22 济南晶正电子科技有限公司 一种复合单晶压电基板及制备方法
CN111477543A (zh) * 2020-04-23 2020-07-31 济南晶正电子科技有限公司 一种键合衬底晶圆与单晶压电晶圆的方法及复合单晶压电晶圆基板
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JP2005252244A (ja) 2004-02-03 2005-09-15 Ishikawajima Harima Heavy Ind Co Ltd 半導体基板の製造方法
JP2006505941A (ja) 2002-11-07 2006-02-16 コミサリヤ・ア・レネルジ・アトミク 同時注入により基板内に脆性領域を生成する方法

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JP2006505941A (ja) 2002-11-07 2006-02-16 コミサリヤ・ア・レネルジ・アトミク 同時注入により基板内に脆性領域を生成する方法
JP2005252244A (ja) 2004-02-03 2005-09-15 Ishikawajima Harima Heavy Ind Co Ltd 半導体基板の製造方法

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JP2009033135A (ja) 2009-02-12
KR20080114512A (ko) 2008-12-31
US7867873B2 (en) 2011-01-11
JP5459987B2 (ja) 2014-04-02
US20090004822A1 (en) 2009-01-01

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