JP5444136B2 - 配線基板 - Google Patents

配線基板 Download PDF

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Publication number
JP5444136B2
JP5444136B2 JP2010139664A JP2010139664A JP5444136B2 JP 5444136 B2 JP5444136 B2 JP 5444136B2 JP 2010139664 A JP2010139664 A JP 2010139664A JP 2010139664 A JP2010139664 A JP 2010139664A JP 5444136 B2 JP5444136 B2 JP 5444136B2
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JP
Japan
Prior art keywords
insulating layer
wiring
layer
insulating
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2010139664A
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English (en)
Japanese (ja)
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JP2012004440A (ja
JP2012004440A5 (enExample
Inventor
人資 近藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2010139664A priority Critical patent/JP5444136B2/ja
Publication of JP2012004440A publication Critical patent/JP2012004440A/ja
Publication of JP2012004440A5 publication Critical patent/JP2012004440A5/ja
Application granted granted Critical
Publication of JP5444136B2 publication Critical patent/JP5444136B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2010139664A 2010-06-18 2010-06-18 配線基板 Active JP5444136B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2010139664A JP5444136B2 (ja) 2010-06-18 2010-06-18 配線基板

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010139664A JP5444136B2 (ja) 2010-06-18 2010-06-18 配線基板

Publications (3)

Publication Number Publication Date
JP2012004440A JP2012004440A (ja) 2012-01-05
JP2012004440A5 JP2012004440A5 (enExample) 2013-06-27
JP5444136B2 true JP5444136B2 (ja) 2014-03-19

Family

ID=45536067

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010139664A Active JP5444136B2 (ja) 2010-06-18 2010-06-18 配線基板

Country Status (1)

Country Link
JP (1) JP5444136B2 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013229526A (ja) * 2012-04-26 2013-11-07 Ngk Spark Plug Co Ltd 多層配線基板及びその製造方法
WO2013175927A1 (ja) 2012-05-24 2013-11-28 富士フイルム株式会社 偏光板及び液晶表示装置
JP5990421B2 (ja) * 2012-07-20 2016-09-14 新光電気工業株式会社 配線基板及びその製造方法、半導体パッケージ
JP5952153B2 (ja) * 2012-09-28 2016-07-13 京セラ株式会社 積層配線基板およびそれを用いた実装構造体
US10424547B2 (en) * 2017-08-30 2019-09-24 Advanced Semiconductor Engineering Inc. Semiconductor device package and a method of manufacturing the same

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04322451A (ja) * 1991-04-23 1992-11-12 Hitachi Ltd 半導体装置
JP2000244127A (ja) * 1998-12-24 2000-09-08 Ngk Spark Plug Co Ltd 配線基板および配線基板の製造方法
JP2000286362A (ja) * 1999-03-30 2000-10-13 Mitsubishi Gas Chem Co Inc 極薄ｂｇａタイプ半導体プラスチックパッケージ用プリント配線板
JP2000294677A (ja) * 1999-04-05 2000-10-20 Fujitsu Ltd 高密度薄膜配線基板及びその製造方法
JP2001284809A (ja) * 2000-04-03 2001-10-12 Ibiden Co Ltd 多層回路基板および、その製造方法
JP3760101B2 (ja) * 2001-02-13 2006-03-29 富士通株式会社 多層プリント配線板およびその製造方法
JP2002290022A (ja) * 2001-03-27 2002-10-04 Kyocera Corp 配線基板およびその製造方法ならびに電子装置
JP4070193B2 (ja) * 2002-10-01 2008-04-02 京セラ株式会社 配線基板および電子部品実装構造体
JP4072176B2 (ja) * 2005-08-29 2008-04-09 新光電気工業株式会社 多層配線基板の製造方法
JP4806279B2 (ja) * 2006-03-17 2011-11-02 三菱樹脂株式会社 ガラスクロス含有絶縁基材
JP4929784B2 (ja) * 2006-03-27 2012-05-09 富士通株式会社 多層配線基板、半導体装置およびソルダレジスト
JP2008028302A (ja) * 2006-07-25 2008-02-07 Sumitomo Bakelite Co Ltd 多層回路基板及び該多層回路基板を用いた半導体装置
JP2008041932A (ja) * 2006-08-07 2008-02-21 Toray Ind Inc 配線基板の製造方法
JP5092547B2 (ja) * 2007-05-30 2012-12-05 凸版印刷株式会社 印刷配線板の製造方法
JP5096855B2 (ja) * 2007-09-27 2012-12-12 新光電気工業株式会社 配線基板の製造方法及び配線基板
JP2009224461A (ja) * 2008-03-14 2009-10-01 Shinko Electric Ind Co Ltd 配線基板及びその製造方法
JP5295596B2 (ja) * 2008-03-19 2013-09-18 新光電気工業株式会社 多層配線基板およびその製造方法
JP5302635B2 (ja) * 2008-11-13 2013-10-02 パナソニック株式会社 多層配線基板

Also Published As

Publication number Publication date
JP2012004440A (ja) 2012-01-05

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