JP5431777B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

Info

Publication number
JP5431777B2
JP5431777B2 JP2009101679A JP2009101679A JP5431777B2 JP 5431777 B2 JP5431777 B2 JP 5431777B2 JP 2009101679 A JP2009101679 A JP 2009101679A JP 2009101679 A JP2009101679 A JP 2009101679A JP 5431777 B2 JP5431777 B2 JP 5431777B2
Authority
JP
Japan
Prior art keywords
wafer
insulating film
film pattern
thickness
back surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2009101679A
Other languages
English (en)
Japanese (ja)
Other versions
JP2010251632A (ja
JP2010251632A5 (https=
Inventor
春男 天田
健二 嶋澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2009101679A priority Critical patent/JP5431777B2/ja
Priority to US12/719,067 priority patent/US8039276B2/en
Publication of JP2010251632A publication Critical patent/JP2010251632A/ja
Priority to US13/237,235 priority patent/US8153452B2/en
Publication of JP2010251632A5 publication Critical patent/JP2010251632A5/ja
Application granted granted Critical
Publication of JP5431777B2 publication Critical patent/JP5431777B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/20—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by the properties tested or measured, e.g. structural or electrical properties
    • H10P74/207—Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7422—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Formation Of Insulating Films (AREA)
JP2009101679A 2009-04-20 2009-04-20 半導体装置の製造方法 Active JP5431777B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2009101679A JP5431777B2 (ja) 2009-04-20 2009-04-20 半導体装置の製造方法
US12/719,067 US8039276B2 (en) 2009-04-20 2010-03-08 Manufacturing method of semiconductor device
US13/237,235 US8153452B2 (en) 2009-04-20 2011-09-20 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009101679A JP5431777B2 (ja) 2009-04-20 2009-04-20 半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2010251632A JP2010251632A (ja) 2010-11-04
JP2010251632A5 JP2010251632A5 (https=) 2012-04-12
JP5431777B2 true JP5431777B2 (ja) 2014-03-05

Family

ID=42981301

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009101679A Active JP5431777B2 (ja) 2009-04-20 2009-04-20 半導体装置の製造方法

Country Status (2)

Country Link
US (2) US8039276B2 (https=)
JP (1) JP5431777B2 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11081344B2 (en) 2018-01-25 2021-08-03 Fujifilm Business Innovation Corp. Method for manufacturing semiconductor substrate

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2953064B1 (fr) * 2009-11-20 2011-12-16 St Microelectronics Tours Sas Procede d'encapsulation de composants electroniques sur tranche
WO2012165551A1 (ja) * 2011-06-02 2012-12-06 電気化学工業株式会社 粘着テープおよび半導体ウエハ加工方法
JP5755043B2 (ja) * 2011-06-20 2015-07-29 株式会社ディスコ 半導体ウエーハの加工方法
JP5846060B2 (ja) * 2011-07-27 2016-01-20 信越化学工業株式会社 ウエハ加工体、ウエハ加工用部材、ウエハ加工用仮接着材、及び薄型ウエハの製造方法
JP5464192B2 (ja) * 2011-09-29 2014-04-09 株式会社デンソー 半導体装置の製造方法
JP5893887B2 (ja) * 2011-10-11 2016-03-23 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP5687647B2 (ja) * 2012-03-14 2015-03-18 株式会社東芝 半導体装置の製造方法、半導体製造装置
JP5591852B2 (ja) * 2012-03-19 2014-09-17 株式会社東芝 半導体装置の検査方法、半導体装置の製造方法、検査用治具
US9318446B2 (en) 2013-03-15 2016-04-19 Infineon Technologies Austria Ag Metal deposition on substrates
JP6304445B2 (ja) * 2015-03-16 2018-04-04 富士電機株式会社 半導体装置の製造方法
WO2016169818A1 (en) * 2015-04-24 2016-10-27 Abb Technology Ag Power semiconductor device with thick top-metal-design and method for manufacturing such power semiconductor device
DE102015112649B4 (de) * 2015-07-31 2021-02-04 Infineon Technologies Ag Verfahren zum bilden eines halbleiterbauelements und halbleiterbauelement
JP6658171B2 (ja) 2016-03-22 2020-03-04 富士電機株式会社 半導体装置の製造方法
CN112437972A (zh) * 2018-01-17 2021-03-02 Spp科技股份有限公司 宽能隙半导体基板、宽能隙半导体基板之制造装置及宽能隙半导体基板之制造方法
JP7200537B2 (ja) * 2018-08-21 2023-01-10 富士フイルムビジネスイノベーション株式会社 半導体基板の製造方法
US20200321236A1 (en) * 2019-04-02 2020-10-08 Semiconductor Components Industries, Llc Edge ring removal methods
CN110676207B (zh) * 2019-09-27 2021-11-16 云谷（固安）科技有限公司 分离装置以及分离方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3184493B2 (ja) * 1997-10-01 2001-07-09 松下電子工業株式会社 電子装置の製造方法
US6162702A (en) * 1999-06-17 2000-12-19 Intersil Corporation Self-supported ultra thin silicon wafer process
JP3834589B2 (ja) * 2001-06-27 2006-10-18 株式会社ルネサステクノロジ 半導体装置の製造方法
US7148125B2 (en) * 2001-12-12 2006-12-12 Denso Corporation Method for manufacturing semiconductor power device
JP3620528B2 (ja) 2001-12-12 2005-02-16 株式会社デンソー 半導体装置の製造方法
US6884717B1 (en) * 2002-01-03 2005-04-26 The United States Of America As Represented By The Secretary Of The Air Force Stiffened backside fabrication for microwave radio frequency wafers
JP2004186522A (ja) * 2002-12-05 2004-07-02 Renesas Technology Corp 半導体装置の製造方法
JP4570896B2 (ja) * 2004-04-06 2010-10-27 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2005303218A (ja) * 2004-04-16 2005-10-27 Renesas Technology Corp 半導体装置およびその製造方法
JP4020097B2 (ja) 2004-05-11 2007-12-12 セイコーエプソン株式会社 半導体チップ、半導体装置及びその製造方法、並びに電子機器
WO2006008824A1 (ja) * 2004-07-16 2006-01-26 Renesas Technology Corp. 半導体集積回路装置の製造方法
JP4904922B2 (ja) 2006-05-26 2012-03-28 トヨタ自動車株式会社 半導体基板製造方法及び半導体基板
JP4816278B2 (ja) * 2006-06-15 2011-11-16 富士電機株式会社 半導体装置の製造方法
JP2008053595A (ja) 2006-08-28 2008-03-06 Toyota Motor Corp 半導体ウエハとその製造方法
JP5007179B2 (ja) * 2007-08-29 2012-08-22 ルネサスエレクトロニクス株式会社 半導体装置の製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11081344B2 (en) 2018-01-25 2021-08-03 Fujifilm Business Innovation Corp. Method for manufacturing semiconductor substrate

Also Published As

Publication number Publication date
JP2010251632A (ja) 2010-11-04
US20100267175A1 (en) 2010-10-21
US8039276B2 (en) 2011-10-18
US20120009695A1 (en) 2012-01-12
US8153452B2 (en) 2012-04-10

Similar Documents

Publication Publication Date Title
JP5431777B2 (ja) 半導体装置の製造方法
JP4185704B2 (ja) 半導体装置の製造方法
US8507362B2 (en) Process of forming ultra thin wafers having an edge support ring
JP5712058B2 (ja) 半導体装置の製造方法
CN111599754B (zh) 一种超薄晶圆加工工艺
CN102130047B (zh) 半导体管芯切单方法
US20140134828A1 (en) Semiconductor die singulation method
CN102013391B (zh) 半导体装置的制造方法
US10032670B2 (en) Plasma dicing of silicon carbide
JP2014007351A (ja) 半導体装置の製造方法
CN102130048B (zh) 半导体管芯切单方法
KR102817685B1 (ko) 반도체-온-절연체(soi) 기판을 형성하는 방법
JP6028325B2 (ja) 半導体装置の製造方法
JP2013093442A (ja) 半導体装置の製造方法
JP2013041919A (ja) 半導体装置の製造方法
CN114823367A (zh) 一种半导体功率器件的制造方法
JP4724729B2 (ja) 半導体装置の製造方法
US20200321236A1 (en) Edge ring removal methods
US11710656B2 (en) Method of forming semiconductor-on-insulator (SOI) substrate
CN103839776A (zh) 半导体结构及其形成方法
TWI843148B (zh) 用於矽上gan晶圓之單粒化的系統及方法
JP2010272676A (ja) 半導体装置の製造方法
CN103887158A (zh) 一种钛硅化合物的非原位制程方法
JP2007266347A (ja) 半導体装置の製造方法
CN110767593A (zh) 一种半导体结构及其形成方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120229

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20120229

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20131007

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20131114

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20131125

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20131205

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

Ref document number: 5431777

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350