JP5421863B2 - 半導体パッケージの製造方法 - Google Patents

半導体パッケージの製造方法 Download PDF

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Publication number
JP5421863B2
JP5421863B2 JP2010146769A JP2010146769A JP5421863B2 JP 5421863 B2 JP5421863 B2 JP 5421863B2 JP 2010146769 A JP2010146769 A JP 2010146769A JP 2010146769 A JP2010146769 A JP 2010146769A JP 5421863 B2 JP5421863 B2 JP 5421863B2
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JP
Japan
Prior art keywords
substrate
substrate material
solder
ball
bonding pad
Prior art date
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Active
Application number
JP2010146769A
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English (en)
Japanese (ja)
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JP2012009782A (ja
JP2012009782A5 (https=
Inventor
功一 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2010146769A priority Critical patent/JP5421863B2/ja
Priority to KR1020110060989A priority patent/KR20120001621A/ko
Priority to US13/166,921 priority patent/US8470643B2/en
Publication of JP2012009782A publication Critical patent/JP2012009782A/ja
Publication of JP2012009782A5 publication Critical patent/JP2012009782A5/ja
Application granted granted Critical
Publication of JP5421863B2 publication Critical patent/JP5421863B2/ja
Priority to KR1020170140195A priority patent/KR101827807B1/ko
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/016—Manufacture or treatment using moulds
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/014—Manufacture or treatment using batch processing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Combinations Of Printed Boards (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Wire Bonding (AREA)
JP2010146769A 2010-06-28 2010-06-28 半導体パッケージの製造方法 Active JP5421863B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2010146769A JP5421863B2 (ja) 2010-06-28 2010-06-28 半導体パッケージの製造方法
KR1020110060989A KR20120001621A (ko) 2010-06-28 2011-06-23 반도체 패키지의 제조 방법
US13/166,921 US8470643B2 (en) 2010-06-28 2011-06-23 Manufacturing method of semiconductor packages
KR1020170140195A KR101827807B1 (ko) 2010-06-28 2017-10-26 반도체 패키지의 제조 방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010146769A JP5421863B2 (ja) 2010-06-28 2010-06-28 半導体パッケージの製造方法

Publications (3)

Publication Number Publication Date
JP2012009782A JP2012009782A (ja) 2012-01-12
JP2012009782A5 JP2012009782A5 (https=) 2013-05-16
JP5421863B2 true JP5421863B2 (ja) 2014-02-19

Family

ID=45352922

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010146769A Active JP5421863B2 (ja) 2010-06-28 2010-06-28 半導体パッケージの製造方法

Country Status (3)

Country Link
US (1) US8470643B2 (https=)
JP (1) JP5421863B2 (https=)
KR (2) KR20120001621A (https=)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9064781B2 (en) 2011-03-03 2015-06-23 Broadcom Corporation Package 3D interconnection and method of making same
US8508045B2 (en) 2011-03-03 2013-08-13 Broadcom Corporation Package 3D interconnection and method of making same
JP5761671B2 (ja) * 2012-01-23 2015-08-12 京セラサーキットソリューションズ株式会社 多数個取り配線基板の組立体および多数個取り配線基板の組立方法
JP2013219170A (ja) * 2012-04-09 2013-10-24 Yokogawa Electric Corp 基板装置
US8809181B2 (en) 2012-11-07 2014-08-19 Intel Corporation Multi-solder techniques and configurations for integrated circuit package assembly
DE102013217301A1 (de) * 2013-08-30 2015-03-05 Robert Bosch Gmbh Bauteil
WO2015079990A1 (ja) * 2013-11-26 2015-06-04 東レエンジニアリング株式会社 実装装置および実装方法
US20190067176A1 (en) * 2016-03-22 2019-02-28 Intel Corporation Void reduction in solder joints using off-eutectic solder
JP6784330B2 (ja) * 2017-06-20 2020-11-11 株式会社村田製作所 モジュールおよびその製造方法
US20190206821A1 (en) * 2017-12-29 2019-07-04 Intel Corporation Substrate assembly with spacer element
CN111029296B (zh) * 2019-11-22 2022-11-22 中国电子科技集团公司第十三研究所 堆叠间距可控的多层基板堆叠结构的制备方法
US11664300B2 (en) * 2019-12-26 2023-05-30 Taiwan Semiconductor Manufacturing Co., Ltd. Fan-out packages and methods of forming the same
JP6767665B1 (ja) * 2020-06-10 2020-10-14 千住金属工業株式会社 バンプ電極基板の形成方法
US11562936B2 (en) 2020-08-31 2023-01-24 Amkor Technology Singapore Holding Pte. Ltd. Electrionic devices with interposer and redistribution layer
JP7661663B2 (ja) 2021-06-10 2025-04-15 新光電気工業株式会社 半導体装置及び半導体装置の製造方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002324952A (ja) * 2001-04-24 2002-11-08 Denso Corp プリント基板
JP2002368369A (ja) * 2001-06-06 2002-12-20 Yamaichi Electronics Co Ltd フレキシブルプリント配線板及びその製造方法
JP3507819B2 (ja) * 2001-10-29 2004-03-15 松下電器産業株式会社 樹脂封止型半導体装置及びその製造方法
JP2004134482A (ja) * 2002-10-09 2004-04-30 Toppan Printing Co Ltd 多層プリント配線板の製造方法
JP2005085825A (ja) * 2003-09-04 2005-03-31 Sony Corp ベアチップと基板との接続構造及びベアチップ用ソケット
JP2006049569A (ja) * 2004-08-04 2006-02-16 Sharp Corp スタック型半導体装置パッケージおよびその製造方法
JP4182144B2 (ja) * 2005-12-14 2008-11-19 新光電気工業株式会社 チップ内蔵基板の製造方法
US7989707B2 (en) 2005-12-14 2011-08-02 Shinko Electric Industries Co., Ltd. Chip embedded substrate and method of producing the same
US20080002460A1 (en) * 2006-03-01 2008-01-03 Tessera, Inc. Structure and method of making lidded chips
JP4949114B2 (ja) * 2007-04-11 2012-06-06 新光電気工業株式会社 接続材料塗布装置および半導体装置の製造方法
JP2009130048A (ja) * 2007-11-21 2009-06-11 Elpida Memory Inc 半導体装置及び電子装置
JP4833192B2 (ja) * 2007-12-27 2011-12-07 新光電気工業株式会社 電子装置
JP5352437B2 (ja) * 2009-11-30 2013-11-27 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US8399300B2 (en) * 2010-04-27 2013-03-19 Stats Chippac, Ltd. Semiconductor device and method of forming adjacent channel and DAM material around die attach area of substrate to control outward flow of underfill material
US10096540B2 (en) * 2011-05-13 2018-10-09 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming dummy pillars between semiconductor die and substrate for maintaining standoff distance
US20130087921A1 (en) * 2011-09-19 2013-04-11 Infineon Technologies Ag Semiconductor Arrangement for Galvanically Isolated Signal Transmission and Method for Producing Such an Arrangement

Also Published As

Publication number Publication date
KR20120001621A (ko) 2012-01-04
KR101827807B1 (ko) 2018-02-09
JP2012009782A (ja) 2012-01-12
KR20170123596A (ko) 2017-11-08
US8470643B2 (en) 2013-06-25
US20110318878A1 (en) 2011-12-29

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