KR20120001621A - 반도체 패키지의 제조 방법 - Google Patents

반도체 패키지의 제조 방법 Download PDF

Info

Publication number
KR20120001621A
KR20120001621A KR1020110060989A KR20110060989A KR20120001621A KR 20120001621 A KR20120001621 A KR 20120001621A KR 1020110060989 A KR1020110060989 A KR 1020110060989A KR 20110060989 A KR20110060989 A KR 20110060989A KR 20120001621 A KR20120001621 A KR 20120001621A
Authority
KR
South Korea
Prior art keywords
substrate
substrate material
solder
ball
bonding pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1020110060989A
Other languages
English (en)
Korean (ko)
Inventor
고이치 다나카
Original Assignee
신꼬오덴기 고교 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 신꼬오덴기 고교 가부시키가이샤 filed Critical 신꼬오덴기 고교 가부시키가이샤
Publication of KR20120001621A publication Critical patent/KR20120001621A/ko
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/016—Manufacture or treatment using moulds
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/014—Manufacture or treatment using batch processing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Combinations Of Printed Boards (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Wire Bonding (AREA)
KR1020110060989A 2010-06-28 2011-06-23 반도체 패키지의 제조 방법 Withdrawn KR20120001621A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2010146769A JP5421863B2 (ja) 2010-06-28 2010-06-28 半導体パッケージの製造方法
JPJP-P-2010-146769 2010-06-28

Related Child Applications (1)

Application Number Title Priority Date Filing Date
KR1020170140195A Division KR101827807B1 (ko) 2010-06-28 2017-10-26 반도체 패키지의 제조 방법

Publications (1)

Publication Number Publication Date
KR20120001621A true KR20120001621A (ko) 2012-01-04

Family

ID=45352922

Family Applications (2)

Application Number Title Priority Date Filing Date
KR1020110060989A Withdrawn KR20120001621A (ko) 2010-06-28 2011-06-23 반도체 패키지의 제조 방법
KR1020170140195A Active KR101827807B1 (ko) 2010-06-28 2017-10-26 반도체 패키지의 제조 방법

Family Applications After (1)

Application Number Title Priority Date Filing Date
KR1020170140195A Active KR101827807B1 (ko) 2010-06-28 2017-10-26 반도체 패키지의 제조 방법

Country Status (3)

Country Link
US (1) US8470643B2 (https=)
JP (1) JP5421863B2 (https=)
KR (2) KR20120001621A (https=)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20130086110A (ko) * 2012-01-23 2013-07-31 쿄세라 에스엘시 테크놀로지 가부시키가이샤 멀티 패턴 배선 기판의 조립체 및 멀티 패턴 배선 기판의 조립 방법
KR20210150598A (ko) * 2017-06-20 2021-12-10 가부시키가이샤 무라타 세이사쿠쇼 모듈 및 그 제조 방법
US11664300B2 (en) 2019-12-26 2023-05-30 Taiwan Semiconductor Manufacturing Co., Ltd. Fan-out packages and methods of forming the same

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9064781B2 (en) 2011-03-03 2015-06-23 Broadcom Corporation Package 3D interconnection and method of making same
US8508045B2 (en) 2011-03-03 2013-08-13 Broadcom Corporation Package 3D interconnection and method of making same
JP2013219170A (ja) * 2012-04-09 2013-10-24 Yokogawa Electric Corp 基板装置
US8809181B2 (en) 2012-11-07 2014-08-19 Intel Corporation Multi-solder techniques and configurations for integrated circuit package assembly
DE102013217301A1 (de) * 2013-08-30 2015-03-05 Robert Bosch Gmbh Bauteil
WO2015079990A1 (ja) * 2013-11-26 2015-06-04 東レエンジニアリング株式会社 実装装置および実装方法
US20190067176A1 (en) * 2016-03-22 2019-02-28 Intel Corporation Void reduction in solder joints using off-eutectic solder
US20190206821A1 (en) * 2017-12-29 2019-07-04 Intel Corporation Substrate assembly with spacer element
CN111029296B (zh) * 2019-11-22 2022-11-22 中国电子科技集团公司第十三研究所 堆叠间距可控的多层基板堆叠结构的制备方法
JP6767665B1 (ja) * 2020-06-10 2020-10-14 千住金属工業株式会社 バンプ電極基板の形成方法
US11562936B2 (en) 2020-08-31 2023-01-24 Amkor Technology Singapore Holding Pte. Ltd. Electrionic devices with interposer and redistribution layer
JP7661663B2 (ja) 2021-06-10 2025-04-15 新光電気工業株式会社 半導体装置及び半導体装置の製造方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002324952A (ja) * 2001-04-24 2002-11-08 Denso Corp プリント基板
JP2002368369A (ja) * 2001-06-06 2002-12-20 Yamaichi Electronics Co Ltd フレキシブルプリント配線板及びその製造方法
JP3507819B2 (ja) * 2001-10-29 2004-03-15 松下電器産業株式会社 樹脂封止型半導体装置及びその製造方法
JP2004134482A (ja) * 2002-10-09 2004-04-30 Toppan Printing Co Ltd 多層プリント配線板の製造方法
JP2005085825A (ja) * 2003-09-04 2005-03-31 Sony Corp ベアチップと基板との接続構造及びベアチップ用ソケット
JP2006049569A (ja) * 2004-08-04 2006-02-16 Sharp Corp スタック型半導体装置パッケージおよびその製造方法
JP4182144B2 (ja) * 2005-12-14 2008-11-19 新光電気工業株式会社 チップ内蔵基板の製造方法
US7989707B2 (en) 2005-12-14 2011-08-02 Shinko Electric Industries Co., Ltd. Chip embedded substrate and method of producing the same
US20080002460A1 (en) * 2006-03-01 2008-01-03 Tessera, Inc. Structure and method of making lidded chips
JP4949114B2 (ja) * 2007-04-11 2012-06-06 新光電気工業株式会社 接続材料塗布装置および半導体装置の製造方法
JP2009130048A (ja) * 2007-11-21 2009-06-11 Elpida Memory Inc 半導体装置及び電子装置
JP4833192B2 (ja) * 2007-12-27 2011-12-07 新光電気工業株式会社 電子装置
JP5352437B2 (ja) * 2009-11-30 2013-11-27 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US8399300B2 (en) * 2010-04-27 2013-03-19 Stats Chippac, Ltd. Semiconductor device and method of forming adjacent channel and DAM material around die attach area of substrate to control outward flow of underfill material
US10096540B2 (en) * 2011-05-13 2018-10-09 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming dummy pillars between semiconductor die and substrate for maintaining standoff distance
US20130087921A1 (en) * 2011-09-19 2013-04-11 Infineon Technologies Ag Semiconductor Arrangement for Galvanically Isolated Signal Transmission and Method for Producing Such an Arrangement

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20130086110A (ko) * 2012-01-23 2013-07-31 쿄세라 에스엘시 테크놀로지 가부시키가이샤 멀티 패턴 배선 기판의 조립체 및 멀티 패턴 배선 기판의 조립 방법
KR20210150598A (ko) * 2017-06-20 2021-12-10 가부시키가이샤 무라타 세이사쿠쇼 모듈 및 그 제조 방법
US11664300B2 (en) 2019-12-26 2023-05-30 Taiwan Semiconductor Manufacturing Co., Ltd. Fan-out packages and methods of forming the same

Also Published As

Publication number Publication date
JP5421863B2 (ja) 2014-02-19
KR101827807B1 (ko) 2018-02-09
JP2012009782A (ja) 2012-01-12
KR20170123596A (ko) 2017-11-08
US8470643B2 (en) 2013-06-25
US20110318878A1 (en) 2011-12-29

Similar Documents

Publication Publication Date Title
KR101827807B1 (ko) 반도체 패키지의 제조 방법
JP4928945B2 (ja) バンプ−オン−リードフリップチップ相互接続
US5863815A (en) Method of manufacturing semiconductor device
CN105643855B (zh) 电子部件、其制造方法及制造装置
US20170110340A1 (en) Leadframe package with pre-applied filler material
JP6400509B2 (ja) 電子部品の製造方法
JP5149881B2 (ja) 半導体装置の製造方法
KR20140098694A (ko) 전자 부품 내장 기판 및 그 제조 방법
JP2008159956A (ja) 電子部品内蔵基板
KR20040100949A (ko) 반도체 패키지의 제조 방법, 및 반도체 장치의 제조 방법
JP2012028484A (ja) モジュールと、その製造方法
CN101156238A (zh) 电子零件连接用突起电极与使用其的电子零件安装体及这些的制造方法
CN104701281A (zh) 电子设备及其制造方法
JP4051570B2 (ja) 半導体装置の製造方法
CN108321092B (zh) 电路部件的制造方法和电路部件
JP2004342802A (ja) 突起電極付きプリント基板およびその製造方法
JP2870533B1 (ja) 半導体装置およびその製造方法
US20070273010A1 (en) Design and Method for Attaching a Die to a Leadframe in a Semiconductor Device
CN105097558A (zh) 芯片封装结构、制作方法及芯片封装基板
KR101681400B1 (ko) 전자 소자 모듈 및 그 제조 방법
JP4591715B2 (ja) 半導体装置の製造方法
JP2012124333A (ja) 半導体装置および半導体装置の製造方法
JP2005116625A (ja) 電子回路基板、電子部品の実装方法、電子部品モジュール及び電子機器
WO2023095447A1 (ja) 電子部品パッケージ、回路モジュール及び電子部品パッケージの製造方法
JP2013219231A (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

A107 Divisional application of patent
PA0107 Divisional application

St.27 status event code: A-0-1-A10-A18-div-PA0107

St.27 status event code: A-0-1-A10-A16-div-PA0107

PC1201 Submission of document of withdrawal after decision of registration

St.27 status event code: N-1-6-B10-B11-nap-PC1201

WITR Withdrawal of patent application after decision to grant
P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000