JP5394625B2 - 配線基板及びその製造方法 - Google Patents

配線基板及びその製造方法 Download PDF

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Publication number
JP5394625B2
JP5394625B2 JP2007261850A JP2007261850A JP5394625B2 JP 5394625 B2 JP5394625 B2 JP 5394625B2 JP 2007261850 A JP2007261850 A JP 2007261850A JP 2007261850 A JP2007261850 A JP 2007261850A JP 5394625 B2 JP5394625 B2 JP 5394625B2
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JP
Japan
Prior art keywords
wiring
reinforcing member
opening
wiring board
connection electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2007261850A
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English (en)
Japanese (ja)
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JP2009094195A5 (enExample
JP2009094195A (ja
Inventor
徳孝 松下
一宏 大島
章夫 堀内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2007261850A priority Critical patent/JP5394625B2/ja
Priority to KR1020080097286A priority patent/KR20090035452A/ko
Priority to TW97138058A priority patent/TWI469287B/zh
Priority to US12/245,025 priority patent/US8410375B2/en
Publication of JP2009094195A publication Critical patent/JP2009094195A/ja
Publication of JP2009094195A5 publication Critical patent/JP2009094195A5/ja
Application granted granted Critical
Publication of JP5394625B2 publication Critical patent/JP5394625B2/ja
Active legal-status Critical Current
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/479—Leadframes on or in insulating or insulated package substrates, interposers, or redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09136—Means for correcting warpage
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/1031—Surface mounted metallic connector elements
    • H05K2201/10318—Surface mounted metallic pins
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10977—Encapsulated connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
    • H05K2203/1305—Moulding and encapsulation
    • H05K2203/1316—Moulded encapsulation of mounted components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7424—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self-supporting substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/655—Fan-out layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Structure Of Printed Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2007261850A 2007-10-05 2007-10-05 配線基板及びその製造方法 Active JP5394625B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2007261850A JP5394625B2 (ja) 2007-10-05 2007-10-05 配線基板及びその製造方法
KR1020080097286A KR20090035452A (ko) 2007-10-05 2008-10-02 배선 기판 및 그 제조 방법
TW97138058A TWI469287B (zh) 2007-10-05 2008-10-03 佈線板及其製造方法
US12/245,025 US8410375B2 (en) 2007-10-05 2008-10-03 Wiring board and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007261850A JP5394625B2 (ja) 2007-10-05 2007-10-05 配線基板及びその製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2013187394A Division JP5712260B2 (ja) 2013-09-10 2013-09-10 配線基板及びその製造方法

Publications (3)

Publication Number Publication Date
JP2009094195A JP2009094195A (ja) 2009-04-30
JP2009094195A5 JP2009094195A5 (enExample) 2010-09-09
JP5394625B2 true JP5394625B2 (ja) 2014-01-22

Family

ID=40533077

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007261850A Active JP5394625B2 (ja) 2007-10-05 2007-10-05 配線基板及びその製造方法

Country Status (4)

Country Link
US (1) US8410375B2 (enExample)
JP (1) JP5394625B2 (enExample)
KR (1) KR20090035452A (enExample)
TW (1) TWI469287B (enExample)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4841609B2 (ja) * 2008-12-01 2011-12-21 第一精工株式会社 配線基板製造用金型およびこれを用いた配線基板の製造方法
JP5313047B2 (ja) * 2009-05-28 2013-10-09 Ｔｏｗａ株式会社 電子部品の樹脂封止用の成形型及び樹脂封止方法
US8742603B2 (en) * 2010-05-20 2014-06-03 Qualcomm Incorporated Process for improving package warpage and connection reliability through use of a backside mold configuration (BSMC)
US8964403B2 (en) * 2010-11-17 2015-02-24 Ngk Spark Plug Co., Ltd. Wiring board having a reinforcing member with capacitors incorporated therein
US8461676B2 (en) 2011-09-09 2013-06-11 Qualcomm Incorporated Soldering relief method and semiconductor device employing same
WO2013065287A1 (ja) * 2011-11-01 2013-05-10 住友ベークライト株式会社 半導体パッケージの製造方法
KR20130097481A (ko) * 2012-02-24 2013-09-03 삼성전자주식회사 인쇄회로기판(ｐｃｂ) 및 그 ｐｃｂ를 포함한 메모리 모듈
US8890284B2 (en) * 2013-02-22 2014-11-18 Infineon Technologies Ag Semiconductor device
US9263329B2 (en) * 2014-03-19 2016-02-16 Intel Corporation Methods of connecting a first electronic package to a second electronic package
US9899238B2 (en) 2014-12-18 2018-02-20 Intel Corporation Low cost package warpage solution
KR102419893B1 (ko) 2018-01-15 2022-07-12 삼성전자주식회사 보호 부재를 가지는 인쇄 회로 기판 및 이를 포함하는 반도체 패키지 제조 방법
JP7202785B2 (ja) * 2018-04-27 2023-01-12 新光電気工業株式会社 配線基板及び配線基板の製造方法
KR102534733B1 (ko) * 2018-07-31 2023-05-19 삼성전자 주식회사 재배선 구조물을 가지는 팬 아웃 반도체 패키지
JP2020031089A (ja) * 2018-08-21 2020-02-27 イビデン株式会社 プリント配線板
JP7362280B2 (ja) * 2019-03-22 2023-10-17 キヤノン株式会社 パッケージユニットの製造方法、パッケージユニット、電子モジュール、および機器
CN111599700B (zh) * 2019-06-20 2022-08-26 矽磐微电子(重庆)有限公司 半导体封装方法及半导体封装结构
TWI690040B (zh) * 2019-07-11 2020-04-01 晶化科技股份有限公司 保護膜片
KR102798695B1 (ko) 2019-08-13 2025-04-24 삼성전자주식회사 반도체 패키지 및 그의 제조 방법
US11224132B2 (en) * 2019-09-06 2022-01-11 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
TWI738069B (zh) * 2019-09-27 2021-09-01 恆勁科技股份有限公司 覆晶封裝基板及其製法
KR102953395B1 (ko) 2021-06-08 2026-04-16 삼성전자주식회사 Pcb 기판을 포함하는 반도체 패키지 제조 방법
KR102901072B1 (ko) * 2023-08-07 2025-12-16 삼성전기주식회사 회로 기판

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11261228A (ja) 1998-03-13 1999-09-24 Ibiden Co Ltd 多層プリント配線板
JP2000058736A (ja) * 1998-08-07 2000-02-25 Sumitomo Kinzoku Electro Device:Kk 樹脂基板へのピン接続方法
JP2000208903A (ja) 1999-01-19 2000-07-28 Ibiden Co Ltd プリント配線板およびその製造方法
JP2000243867A (ja) 1999-02-24 2000-09-08 Hitachi Ltd 半導体装置及びその製造方法並びに半導体装置の積層構造並びに半導体装置の実装構造
JP3635219B2 (ja) 1999-03-11 2005-04-06 新光電気工業株式会社 半導体装置用多層基板及びその製造方法
EP1194022B1 (en) * 1999-06-02 2006-11-02 Ibiden Co., Ltd. Multilayer printed wiring board and method of manufacturing multilayer printed wiring board
JP2001223295A (ja) 2000-02-08 2001-08-17 Hitachi Chem Co Ltd 半導体素子支持基板及びその製造方法並びにそれを用いた半導体装置
JP4427874B2 (ja) 2000-07-06 2010-03-10 住友ベークライト株式会社 多層配線板の製造方法および多層配線板
JP2002151853A (ja) 2000-11-08 2002-05-24 Matsushita Electric Ind Co Ltd 多層配線基板とその製造方法
KR101107976B1 (ko) * 2004-02-04 2012-01-30 이비덴 가부시키가이샤 다층프린트배선판
JP2006332321A (ja) 2005-05-26 2006-12-07 Fujitsu Ltd 半導体装置及びその製造方法
JP4509972B2 (ja) * 2005-09-01 2010-07-21 日本特殊陶業株式会社 配線基板、埋め込み用セラミックチップ
JP4802666B2 (ja) 2005-11-08 2011-10-26 住友金属鉱山株式会社 エポキシ樹脂接着組成物及びそれを用いた光半導体用接着剤
JP2007081437A (ja) 2006-12-21 2007-03-29 Nec Toppan Circuit Solutions Inc 印刷配線板の製造方法

Also Published As

Publication number Publication date
US8410375B2 (en) 2013-04-02
KR20090035452A (ko) 2009-04-09
TW200919671A (en) 2009-05-01
TWI469287B (zh) 2015-01-11
US20090095518A1 (en) 2009-04-16
JP2009094195A (ja) 2009-04-30

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