JP5367523B2 - 配線基板及び配線基板の製造方法 - Google Patents
配線基板及び配線基板の製造方法 Download PDFInfo
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- JP5367523B2 JP5367523B2 JP2009221078A JP2009221078A JP5367523B2 JP 5367523 B2 JP5367523 B2 JP 5367523B2 JP 2009221078 A JP2009221078 A JP 2009221078A JP 2009221078 A JP2009221078 A JP 2009221078A JP 5367523 B2 JP5367523 B2 JP 5367523B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L2924/01005—Boron [B]
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- H01L2924/01013—Aluminum [Al]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/01029—Copper [Cu]
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12044—OLED
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009221078A JP5367523B2 (ja) | 2009-09-25 | 2009-09-25 | 配線基板及び配線基板の製造方法 |
| US12/884,271 US8212365B2 (en) | 2009-09-25 | 2010-09-17 | Printed wiring board and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009221078A JP5367523B2 (ja) | 2009-09-25 | 2009-09-25 | 配線基板及び配線基板の製造方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2011071315A JP2011071315A (ja) | 2011-04-07 |
| JP2011071315A5 JP2011071315A5 (enExample) | 2012-08-23 |
| JP5367523B2 true JP5367523B2 (ja) | 2013-12-11 |
Family
ID=43779399
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2009221078A Active JP5367523B2 (ja) | 2009-09-25 | 2009-09-25 | 配線基板及び配線基板の製造方法 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US8212365B2 (enExample) |
| JP (1) | JP5367523B2 (enExample) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2013000995A (ja) * | 2011-06-17 | 2013-01-07 | Panasonic Corp | 金属張積層板、及びプリント配線板 |
| JP5833398B2 (ja) * | 2011-06-27 | 2015-12-16 | 新光電気工業株式会社 | 配線基板及びその製造方法、半導体装置 |
| JP5561254B2 (ja) * | 2011-07-29 | 2014-07-30 | 株式会社村田製作所 | 回路モジュール及び複合回路モジュール |
| US8780576B2 (en) | 2011-09-14 | 2014-07-15 | Invensas Corporation | Low CTE interposer |
| US8836478B2 (en) * | 2011-09-25 | 2014-09-16 | Authentec, Inc. | Electronic device including finger sensor and related methods |
| JP5778557B2 (ja) * | 2011-11-28 | 2015-09-16 | 新光電気工業株式会社 | 半導体装置の製造方法、半導体装置、及び半導体素子 |
| JP2013123907A (ja) * | 2011-12-16 | 2013-06-24 | Panasonic Corp | 金属張積層板、及びプリント配線板 |
| US9159649B2 (en) * | 2011-12-20 | 2015-10-13 | Intel Corporation | Microelectronic package and stacked microelectronic assembly and computing system containing same |
| JP2013243263A (ja) * | 2012-05-21 | 2013-12-05 | Internatl Business Mach Corp <Ibm> | 3次元積層パッケージにおける電力供給と放熱(冷却)との両立 |
| TWI543283B (zh) * | 2014-07-18 | 2016-07-21 | 矽品精密工業股份有限公司 | 中介基板之製法 |
| KR20170067426A (ko) * | 2015-12-08 | 2017-06-16 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지의 제조 방법 및 이를 이용한 반도체 패키지 |
| EP3394880B1 (en) * | 2015-12-23 | 2022-08-17 | Intel Corporation | Multi-layer molded substrate with graded cte |
| DE102020205686A1 (de) | 2020-05-06 | 2021-11-11 | Robert Bosch Gesellschaft mit beschränkter Haftung | Elektronikvorrichtung |
| JPWO2024154790A1 (enExample) * | 2023-01-19 | 2024-07-25 |
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| US4888247A (en) * | 1986-08-27 | 1989-12-19 | General Electric Company | Low-thermal-expansion, heat conducting laminates having layers of metal and reinforced polymer matrix composite |
| JP2574902B2 (ja) | 1989-09-20 | 1997-01-22 | 株式会社日立製作所 | 半導体装置 |
| JP2783359B2 (ja) * | 1994-11-16 | 1998-08-06 | 日本ピラー工業株式会社 | フッ素樹脂多層回路基板 |
| JPH08167630A (ja) * | 1994-12-15 | 1996-06-25 | Hitachi Ltd | チップ接続構造 |
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2009
- 2009-09-25 JP JP2009221078A patent/JP5367523B2/ja active Active
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2010
- 2010-09-17 US US12/884,271 patent/US8212365B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| US20110074046A1 (en) | 2011-03-31 |
| US8212365B2 (en) | 2012-07-03 |
| JP2011071315A (ja) | 2011-04-07 |
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