JP5367523B2 - 配線基板及び配線基板の製造方法 - Google Patents

配線基板及び配線基板の製造方法 Download PDF

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Publication number
JP5367523B2
JP5367523B2 JP2009221078A JP2009221078A JP5367523B2 JP 5367523 B2 JP5367523 B2 JP 5367523B2 JP 2009221078 A JP2009221078 A JP 2009221078A JP 2009221078 A JP2009221078 A JP 2009221078A JP 5367523 B2 JP5367523 B2 JP 5367523B2
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layer
wiring
wiring board
organic substrate
laminate
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Japanese (ja)
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JP2011071315A5 (enExample
JP2011071315A (ja
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昌宏 春原
啓介 上田
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Priority to JP2009221078A priority Critical patent/JP5367523B2/ja
Priority to US12/884,271 priority patent/US8212365B2/en
Publication of JP2011071315A publication Critical patent/JP2011071315A/ja
Publication of JP2011071315A5 publication Critical patent/JP2011071315A5/ja
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822Multilayer substrates
    • HELECTRICITY
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894Materials of the insulating layers or coatings
    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81192Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • HELECTRICITY
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701Low temperature co-fired ceramic [LTCC]
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
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    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2009221078A 2009-09-25 2009-09-25 配線基板及び配線基板の製造方法 Active JP5367523B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2009221078A JP5367523B2 (ja) 2009-09-25 2009-09-25 配線基板及び配線基板の製造方法
US12/884,271 US8212365B2 (en) 2009-09-25 2010-09-17 Printed wiring board and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009221078A JP5367523B2 (ja) 2009-09-25 2009-09-25 配線基板及び配線基板の製造方法

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JP2011071315A JP2011071315A (ja) 2011-04-07
JP2011071315A5 JP2011071315A5 (enExample) 2012-08-23
JP5367523B2 true JP5367523B2 (ja) 2013-12-11

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Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013000995A (ja) * 2011-06-17 2013-01-07 Panasonic Corp 金属張積層板、及びプリント配線板
JP5833398B2 (ja) * 2011-06-27 2015-12-16 新光電気工業株式会社 配線基板及びその製造方法、半導体装置
JP5561254B2 (ja) * 2011-07-29 2014-07-30 株式会社村田製作所 回路モジュール及び複合回路モジュール
US8780576B2 (en) 2011-09-14 2014-07-15 Invensas Corporation Low CTE interposer
US8836478B2 (en) * 2011-09-25 2014-09-16 Authentec, Inc. Electronic device including finger sensor and related methods
JP5778557B2 (ja) * 2011-11-28 2015-09-16 新光電気工業株式会社 半導体装置の製造方法、半導体装置、及び半導体素子
JP2013123907A (ja) * 2011-12-16 2013-06-24 Panasonic Corp 金属張積層板、及びプリント配線板
US9159649B2 (en) * 2011-12-20 2015-10-13 Intel Corporation Microelectronic package and stacked microelectronic assembly and computing system containing same
JP2013243263A (ja) * 2012-05-21 2013-12-05 Internatl Business Mach Corp <Ibm> 3次元積層パッケージにおける電力供給と放熱(冷却)との両立
TWI543283B (zh) * 2014-07-18 2016-07-21 矽品精密工業股份有限公司 中介基板之製法
KR20170067426A (ko) * 2015-12-08 2017-06-16 앰코 테크놀로지 코리아 주식회사 반도체 패키지의 제조 방법 및 이를 이용한 반도체 패키지
EP3394880B1 (en) * 2015-12-23 2022-08-17 Intel Corporation Multi-layer molded substrate with graded cte
DE102020205686A1 (de) 2020-05-06 2021-11-11 Robert Bosch Gesellschaft mit beschränkter Haftung Elektronikvorrichtung
JPWO2024154790A1 (enExample) * 2023-01-19 2024-07-25

Family Cites Families (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4888247A (en) * 1986-08-27 1989-12-19 General Electric Company Low-thermal-expansion, heat conducting laminates having layers of metal and reinforced polymer matrix composite
JP2574902B2 (ja) 1989-09-20 1997-01-22 株式会社日立製作所 半導体装置
JP2783359B2 (ja) * 1994-11-16 1998-08-06 日本ピラー工業株式会社 フッ素樹脂多層回路基板
JPH08167630A (ja) * 1994-12-15 1996-06-25 Hitachi Ltd チップ接続構造
US5888631A (en) * 1996-11-08 1999-03-30 W. L. Gore & Associates, Inc. Method for minimizing warp in the production of electronic assemblies
MY139405A (en) * 1998-09-28 2009-09-30 Ibiden Co Ltd Printed circuit board and method for its production
US6333857B1 (en) * 1998-12-25 2001-12-25 Ngk Spark Plug Co., Ltd. Printing wiring board, core substrate, and method for fabricating the core substrate
US7245647B2 (en) * 1999-10-28 2007-07-17 Ricoh Company, Ltd. Surface-emission laser diode operable in the wavelength band of 1.1-1.7mum and optical telecommunication system using such a laser diode
US6975663B2 (en) * 2001-02-26 2005-12-13 Ricoh Company, Ltd. Surface-emission laser diode operable in the wavelength band of 1.1-7μm and optical telecommunication system using such a laser diode
TW512653B (en) * 1999-11-26 2002-12-01 Ibiden Co Ltd Multilayer circuit board and semiconductor device
WO2001063984A1 (en) * 2000-02-22 2001-08-30 Ppg Industries Ohio, Inc. Electronic supports and methods and apparatus for forming apertures in electronic supports
US6734540B2 (en) * 2000-10-11 2004-05-11 Altera Corporation Semiconductor package with stress inhibiting intermediate mounting substrate
JP3858660B2 (ja) * 2001-10-10 2006-12-20 株式会社日立製作所 樹脂の熱抵抗測定方法
JP4203435B2 (ja) * 2003-05-16 2009-01-07 日本特殊陶業株式会社 多層樹脂配線基板
JP2004356569A (ja) * 2003-05-30 2004-12-16 Shinko Electric Ind Co Ltd 半導体装置用パッケージ
JP2005050879A (ja) * 2003-07-29 2005-02-24 Kyocera Corp 積層型配線基板および電気装置並びにその実装構造
JP2005050878A (ja) * 2003-07-29 2005-02-24 Kyocera Corp 積層型配線基板および電気装置並びにその実装構造
KR20120104641A (ko) * 2004-02-04 2012-09-21 이비덴 가부시키가이샤 다층프린트배선판
TWI280657B (en) * 2004-05-28 2007-05-01 Sanyo Electric Co Circuit device
JP2006253631A (ja) * 2005-02-14 2006-09-21 Fujitsu Ltd 半導体装置及びその製造方法、キャパシタ構造体及びその製造方法
US7253518B2 (en) * 2005-06-15 2007-08-07 Endicott Interconnect Technologies, Inc. Wirebond electronic package with enhanced chip pad design, method of making same, and information handling system utilizing same
US7932471B2 (en) * 2005-08-05 2011-04-26 Ngk Spark Plug Co., Ltd. Capacitor for incorporation in wiring board, wiring board, method of manufacturing wiring board, and ceramic chip for embedment
JP4452222B2 (ja) * 2005-09-07 2010-04-21 新光電気工業株式会社 多層配線基板及びその製造方法
JP5089880B2 (ja) * 2005-11-30 2012-12-05 日本特殊陶業株式会社 配線基板内蔵用キャパシタ、キャパシタ内蔵配線基板及びその製造方法
US20070126085A1 (en) * 2005-12-02 2007-06-07 Nec Electronics Corporation Semiconductor device and method of manufacturing the same
US8279131B2 (en) * 2006-09-21 2012-10-02 Raytheon Company Panel array
JP5068060B2 (ja) * 2006-10-30 2012-11-07 新光電気工業株式会社 半導体パッケージおよびその製造方法
EP2087510A4 (en) * 2006-11-27 2010-05-05 Nikon Corp OPTICAL ELEMENT, ASSOCIATED EXPOSURE UNIT AND METHOD FOR PRODUCING THE DEVICE
JP5311609B2 (ja) * 2007-10-30 2013-10-09 新光電気工業株式会社 シリコンインターポーザの製造方法およびシリコンインターポーザと、これを用いた半導体装置用パッケージおよび半導体装置
JP5079456B2 (ja) * 2007-11-06 2012-11-21 新光電気工業株式会社 半導体装置及びその製造方法
JP4932744B2 (ja) * 2008-01-09 2012-05-16 新光電気工業株式会社 配線基板及びその製造方法並びに電子部品装置及びその製造方法
JP5000540B2 (ja) * 2008-01-31 2012-08-15 新光電気工業株式会社 スイッチング機能付配線基板
JP4981712B2 (ja) * 2008-02-29 2012-07-25 新光電気工業株式会社 配線基板の製造方法及び半導体パッケージの製造方法
CA2726993C (en) * 2008-06-04 2021-06-08 G. Patel A monitoring system based on etching of metals
JP5032456B2 (ja) * 2008-08-12 2012-09-26 新光電気工業株式会社 半導体装置、インターポーザ、及びそれらの製造方法
US9226391B2 (en) * 2009-01-27 2015-12-29 Littelfuse, Inc. Substrates having voltage switchable dielectric materials
JP5247880B2 (ja) * 2009-03-30 2013-07-24 京セラ株式会社 光電気配線基板および光モジュール

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US8212365B2 (en) 2012-07-03
JP2011071315A (ja) 2011-04-07

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