JP5319533B2 - 転写可能な半導体構造、デバイス、及びデバイスコンポーネントを作成するための剥離方法 - Google Patents

転写可能な半導体構造、デバイス、及びデバイスコンポーネントを作成するための剥離方法 Download PDF

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JP5319533B2
JP5319533B2 JP2009529401A JP2009529401A JP5319533B2 JP 5319533 B2 JP5319533 B2 JP 5319533B2 JP 2009529401 A JP2009529401 A JP 2009529401A JP 2009529401 A JP2009529401 A JP 2009529401A JP 5319533 B2 JP5319533 B2 JP 5319533B2
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layer
layers
substrate
functional
multilayer structure
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JP2010504649A (ja
JP2010504649A5 (enExample
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ジョン エー． ロジャース，
ラルフ， ジー． ヌッツォ，
マシュー メイトル，
ヒョン チョ コー，
ジョンスン ユン，
エティエンヌ メナード，
アルフレッド， ジェイ． バカ，
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ザ ボード オブ トラスティーズ オブ ザ ユニヴァーシティー オブ イリノイ
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    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/16—Photovoltaic cells having only PN heterojunction potential barriers
    • H10F10/163—Photovoltaic cells having only PN heterojunction potential barriers comprising only Group III-V materials, e.g. GaAs/AlGaAs or InP/GaInAs photovoltaic cells
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
    • B81C1/00444—Surface micromachining, i.e. structuring layers on the substrate
    • B81C1/0046—Surface micromachining, i.e. structuring layers on the substrate using stamping, e.g. imprinting
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y20/00—Nanooptics, e.g. quantum optics or photonic crystals
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
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    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/7806—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate
    • H01L21/7813—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate leaving a reusable substrate, e.g. epitaxial lift off
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    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/81—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation
    • H10D62/815—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW]
    • H10D62/8161—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW] potential variation due to variations in composition or crystallinity, e.g. heterojunction superlattices
    • H10D62/8162—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW] potential variation due to variations in composition or crystallinity, e.g. heterojunction superlattices having quantum effects only in the vertical direction, i.e. layered structures having quantum effects solely resulting from vertical potential variation
    • H10D62/8164—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW] potential variation due to variations in composition or crystallinity, e.g. heterojunction superlattices having quantum effects only in the vertical direction, i.e. layered structures having quantum effects solely resulting from vertical potential variation comprising only semiconductor materials 
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    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/824—Heterojunctions comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
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    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
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    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/05—Manufacture or treatment characterised by using material-based technologies using Group III-V technology
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    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/14—Photovoltaic cells having only PN homojunction potential barriers
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    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/14—Photovoltaic cells having only PN homojunction potential barriers
    • H10F10/142—Photovoltaic cells having only PN homojunction potential barriers comprising multiple PN homojunctions, e.g. tandem cells
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    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
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    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/16—Photovoltaic cells having only PN heterojunction potential barriers
    • H10F10/161—Photovoltaic cells having only PN heterojunction potential barriers comprising multiple PN heterojunctions, e.g. tandem cells
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    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/127—The active layers comprising only Group III-V materials, e.g. GaAs or InP
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    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/127—The active layers comprising only Group III-V materials, e.g. GaAs or InP
    • H10F71/1272—The active layers comprising only Group III-V materials, e.g. GaAs or InP comprising at least three elements, e.g. GaAlAs or InGaAsP
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    • H10F77/10—Semiconductor bodies
    • H10F77/12—Active materials
    • H10F77/124—Active materials comprising only Group III-V materials, e.g. GaAs
    • H10F77/1248—Active materials comprising only Group III-V materials, e.g. GaAs having three or more elements, e.g. GaAlAs, InGaAs or InGaAsP
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    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0174—Manufacture or treatment of microstructural devices or systems in or on a substrate for making multi-layered devices, film deposition or growing
    • B81C2201/0191—Transfer of a layer from a carrier wafer to a device wafer
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    • H01L2221/68368—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/95001—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
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    • H10H20/01—Manufacture or treatment
    • H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
    • H10H20/018—Bonding of wafers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
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JP2009529401A 2006-09-20 2007-09-20 転写可能な半導体構造、デバイス、及びデバイスコンポーネントを作成するための剥離方法 Active JP5319533B2 (ja)

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US82635406P 2006-09-20 2006-09-20
US60/826,354 2006-09-20
US94465307P 2007-06-18 2007-06-18
US60/944,653 2007-06-18
PCT/US2007/079070 WO2008036837A2 (en) 2006-09-20 2007-09-20 Release strategies for making transferable semiconductor structures, devices and device components

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JP2010504649A5 JP2010504649A5 (enExample) 2010-10-21
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JP2013144886A Active JP5805712B2 (ja) 2006-09-20 2013-07-10 転写可能な半導体構造、デバイス、及びデバイスコンポーネントを作成するための剥離方法
JP2015172848A Active JP6238141B2 (ja) 2006-09-20 2015-09-02 転写可能な半導体構造、デバイス、及びデバイスコンポーネントを作成するための剥離方法

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JP2015172848A Active JP6238141B2 (ja) 2006-09-20 2015-09-02 転写可能な半導体構造、デバイス、及びデバイスコンポーネントを作成するための剥離方法

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WO2022091670A1 (ja) 2020-10-30 2022-05-05 信越化学工業株式会社 発光ダイオード供給基板の製造方法、発光ダイオードディスプレイの製造方法、発光ダイオードディスプレイの分割ユニットの製造方法、及び素子供給基板の製造方法
KR20250100771A (ko) 2020-10-30 2025-07-03 신에쓰 가가꾸 고교 가부시끼가이샤 발광다이오드 공급기판의 제조방법, 발광다이오드 디스플레이의 제조방법, 발광다이오드 디스플레이의 분할유닛의 제조방법, 및 소자 공급기판의 제조방법

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