JP5250597B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP5250597B2 JP5250597B2 JP2010219825A JP2010219825A JP5250597B2 JP 5250597 B2 JP5250597 B2 JP 5250597B2 JP 2010219825 A JP2010219825 A JP 2010219825A JP 2010219825 A JP2010219825 A JP 2010219825A JP 5250597 B2 JP5250597 B2 JP 5250597B2
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- layer
- copper
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Thin Film Transistor (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Recrystallisation Techniques (AREA)
- Electrodes Of Semiconductors (AREA)
Description
まず、図1(c)に示すように、表面が比較的平坦な下地バリア層3上に、銅を主成分とする金属シード層、例えば銅シード層4が成膜される。この銅シード層4の成膜法としては、例えばスパッタリング法を用いることができる。銅シード層4は、例えば30nm〜300nmの厚さに形成される。銅シード層4は、結晶面の結晶方位が主として(111)に配向していることが望ましい。
次に、図2(c)に示すように、銅シード層4の上に銅薄膜、例えば銅配線層7を無電解めっき法で形成する。無電解めっき法では、電解めっき法と異なり、電界をかけるための配線形成及びその後の工程での切断工程が不要である。また、電界を付与するための装置が不要であるため、基板1の1辺サイズが1メートルを越える矩形基板でも均一な成膜が可能である。銅配線層7の厚さは、例えば400nmである。銅配線層7は、図2(c)に示すように、銅シード層4の表面上のみに成膜される。
Claims (10)
- ガラス基板上に薄膜トランジスタ及び配線を有する半導体装置を製造する方法において、
ガラス基板上に下地絶縁層を形成する工程と、
前記下地絶縁層上に下地バリア層を形成する工程と、
前記下地バリア層上にシード層を形成する工程と、
前記シード層を前記配線に対応する形状にパターニングしてシード層パターンを形成する工程と、
前記シード層パターンの表面に銅配線層を無電解めっき法で形成する工程と、
前記銅配線層マスクとして前記下地バリア層をパターニングする工程と、
前記銅配線層を被覆するように銅の拡散に対してバリア性を有する材料からなる絶縁層を形成する工程と、
を備えたことを特徴する半導体装置の製造方法。 - 前記下地絶縁層は、窒化シリコン膜を含むことを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記下地バリア層は、Ta,TaN,TiN,TaSiNの少なくとも1つの層からなるバリアメタルであることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記シード層は、銅を主成分とする銅シード層であることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記シード層は、Mg,Ta,Ti,Mo,Mn,Al,W,Zrの少なくとも一つ以上の金属を含む銅合金シード層であることを特徴とする請求項4に記載の半導体装置の製造方法。
- 前記シード層と前記下地絶縁層との界面に酸化物層を形成する工程を含むことを特徴とする請求項5に記載の半導体装置の製造方法。
- 前記酸化物層はMgO,TiO2,Ta2O5から選ばれることを特徴とする請求項5に記載の半導体装置の製造方法。
- 前記シード層は、結晶面の結晶方位が(111)に配向していることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記銅配線層の膜厚は200〜1000nmであり、比抵抗が2.5μΩcm以下であることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記銅配線層を500℃以下の非酸化性雰囲気中でアニールする工程を含むことを特徴とする請求項1に記載の半導体装置の製造方法。
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