JP5224845B2 - 半導体装置の製造方法及び半導体装置 - Google Patents

半導体装置の製造方法及び半導体装置 Download PDF

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JP5224845B2
JP5224845B2 JP2008036235A JP2008036235A JP5224845B2 JP 5224845 B2 JP5224845 B2 JP 5224845B2 JP 2008036235 A JP2008036235 A JP 2008036235A JP 2008036235 A JP2008036235 A JP 2008036235A JP 5224845 B2 JP5224845 B2 JP 5224845B2
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semiconductor device
metal
support substrate
modification
semiconductor chip
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JP2009194322A5 (enExample
JP2009194322A (ja
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章夫 堀内
俊次 宮坂
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Priority to JP2008036235A priority Critical patent/JP5224845B2/ja
Priority to KR1020090013080A priority patent/KR101602958B1/ko
Priority to US12/372,198 priority patent/US8217509B2/en
Priority to TW098105083A priority patent/TWI497617B/zh
Priority to CN2009100069877A priority patent/CN101515554B/zh
Publication of JP2009194322A publication Critical patent/JP2009194322A/ja
Publication of JP2009194322A5 publication Critical patent/JP2009194322A5/ja
Priority to US13/162,071 priority patent/US9048242B2/en
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
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    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

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  • Engineering & Computer Science (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
JP2008036235A 2008-02-18 2008-02-18 半導体装置の製造方法及び半導体装置 Active JP5224845B2 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2008036235A JP5224845B2 (ja) 2008-02-18 2008-02-18 半導体装置の製造方法及び半導体装置
US12/372,198 US8217509B2 (en) 2008-02-18 2009-02-17 Semiconductor device
KR1020090013080A KR101602958B1 (ko) 2008-02-18 2009-02-17 반도체 장치의 제조 방법, 반도체 장치 및 배선 기판
CN2009100069877A CN101515554B (zh) 2008-02-18 2009-02-18 半导体器件的制造方法、半导体器件以及配线基板
TW098105083A TWI497617B (zh) 2008-02-18 2009-02-18 半導體裝置之製造方法及半導體裝置
US13/162,071 US9048242B2 (en) 2008-02-18 2011-06-16 Semiconductor device manufacturing method, semiconductor device, and wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008036235A JP5224845B2 (ja) 2008-02-18 2008-02-18 半導体装置の製造方法及び半導体装置

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JP2009194322A JP2009194322A (ja) 2009-08-27
JP2009194322A5 JP2009194322A5 (enExample) 2011-02-10
JP5224845B2 true JP5224845B2 (ja) 2013-07-03

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US (2) US8217509B2 (enExample)
JP (1) JP5224845B2 (enExample)
KR (1) KR101602958B1 (enExample)
CN (1) CN101515554B (enExample)
TW (1) TWI497617B (enExample)

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JP5355363B2 (ja) * 2009-11-30 2013-11-27 新光電気工業株式会社 半導体装置内蔵基板及びその製造方法
KR101141209B1 (ko) * 2010-02-01 2012-05-04 삼성전기주식회사 단층 인쇄회로기판 및 그 제조방법
US8319318B2 (en) * 2010-04-06 2012-11-27 Intel Corporation Forming metal filled die back-side film for electromagnetic interference shielding with coreless packages
US8618652B2 (en) 2010-04-16 2013-12-31 Intel Corporation Forming functionalized carrier structures with coreless packages
JP2012146963A (ja) * 2010-12-20 2012-08-02 Shinko Electric Ind Co Ltd 半導体パッケージの製造方法及び半導体パッケージ
JP2013114415A (ja) 2011-11-28 2013-06-10 Elpida Memory Inc メモリモジュール
KR101333893B1 (ko) * 2012-01-03 2013-11-27 주식회사 네패스 반도체 패키지 및 그 제조 방법
US20150035163A1 (en) * 2013-08-02 2015-02-05 Siliconware Precision Industries Co., Ltd. Semiconductor package and method of fabricating the same
TWI582913B (zh) * 2013-08-02 2017-05-11 矽品精密工業股份有限公司 半導體封裝件及其製法
TWI515841B (zh) * 2013-08-02 2016-01-01 矽品精密工業股份有限公司 半導體封裝件及其製法
CN105934823A (zh) 2013-11-27 2016-09-07 At&S奥地利科技与系统技术股份公司 印刷电路板结构
AT515101B1 (de) 2013-12-12 2015-06-15 Austria Tech & System Tech Verfahren zum Einbetten einer Komponente in eine Leiterplatte
US11523520B2 (en) * 2014-02-27 2022-12-06 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Method for making contact with a component embedded in a printed circuit board
TWI557853B (zh) * 2014-11-12 2016-11-11 矽品精密工業股份有限公司 半導體封裝件及其製法
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