JP5188686B2 - Ｎａｎｄ型フラッシュメモリ装置及びその製造方法 - Google Patents

Ｎａｎｄ型フラッシュメモリ装置及びその製造方法 Download PDF

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Publication number
JP5188686B2
JP5188686B2 JP2006190577A JP2006190577A JP5188686B2 JP 5188686 B2 JP5188686 B2 JP 5188686B2 JP 2006190577 A JP2006190577 A JP 2006190577A JP 2006190577 A JP2006190577 A JP 2006190577A JP 5188686 B2 JP5188686 B2 JP 5188686B2
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insulating film
selection
transistor region
low voltage
nand flash
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Japanese (ja)
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JP2007027726A5 (enExample
JP2007027726A (ja
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在▲ヒュク▼ 宋
定▲ヒュク▼ 崔
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

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  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
JP2006190577A 2005-07-12 2006-07-11 Ｎａｎｄ型フラッシュメモリ装置及びその製造方法 Expired - Fee Related JP5188686B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2005-0062792 2005-07-12
KR1020050062792A KR101094840B1 (ko) 2005-07-12 2005-07-12 낸드형 플래시 메모리 장치 및 그 제조 방법

Publications (3)

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JP2007027726A JP2007027726A (ja) 2007-02-01
JP2007027726A5 JP2007027726A5 (enExample) 2009-08-27
JP5188686B2 true JP5188686B2 (ja) 2013-04-24

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JP2006190577A Expired - Fee Related JP5188686B2 (ja) 2005-07-12 2006-07-11 Ｎａｎｄ型フラッシュメモリ装置及びその製造方法

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US (1) US7283393B2 (enExample)
JP (1) JP5188686B2 (enExample)
KR (1) KR101094840B1 (enExample)
CN (1) CN100595925C (enExample)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7755132B2 (en) * 2006-08-16 2010-07-13 Sandisk Corporation Nonvolatile memories with shaped floating gates
WO2008126177A1 (ja) * 2007-03-14 2008-10-23 Fujitsu Microelectronics Limited 不揮発性半導体記憶装置及びその製造方法
JP4564511B2 (ja) * 2007-04-16 2010-10-20 株式会社東芝 半導体装置及びその製造方法
KR100858293B1 (ko) * 2007-10-01 2008-09-11 최웅림 Ｎａｎｄ 메모리 셀 어레이, 상기 ｎａｎｄ 메모리 셀어레이를 구비하는 ｎａｎｄ 플래시 메모리 및 ｎａｎｄ플래시 메모리의 데이터 처리방법
KR100939407B1 (ko) * 2008-02-26 2010-01-28 주식회사 하이닉스반도체 플래시 메모리 소자 및 그의 제조 방법
WO2009139101A1 (ja) * 2008-05-13 2009-11-19 パナソニック株式会社 電子機器システム、および半導体集積回路のコントローラ
CN101640188B (zh) * 2008-08-01 2011-07-13 中芯国际集成电路制造(上海)有限公司 闪存中源极和漏极的制作方法
US8541832B2 (en) 2009-07-23 2013-09-24 Samsung Electronics Co., Ltd. Integrated circuit memory devices having vertical transistor arrays therein and methods of forming same
US20110221006A1 (en) * 2010-03-11 2011-09-15 Spansion Llc Nand array source/drain doping scheme
KR101763420B1 (ko) 2010-09-16 2017-08-01 삼성전자주식회사 3차원 반도체 기억 소자 및 그 제조 방법
KR20130019242A (ko) * 2011-08-16 2013-02-26 에스케이하이닉스 주식회사 반도체 소자 및 그 제조방법
WO2013043602A2 (en) 2011-09-19 2013-03-28 SanDisk Technologies, Inc. High endurance non-volatile storage
TWI469270B (zh) * 2012-01-09 2015-01-11 Winbond Electronics Corp 反及閘型快閃記憶裝置之製造方法
US9224475B2 (en) * 2012-08-23 2015-12-29 Sandisk Technologies Inc. Structures and methods for making NAND flash memory
US9245898B2 (en) 2014-06-30 2016-01-26 Sandisk Technologies Inc. NAND flash memory integrated circuits and processes with controlled gate height
US9224637B1 (en) 2014-08-26 2015-12-29 Sandisk Technologies Inc. Bi-level dry etching scheme for transistor contacts
US9443862B1 (en) 2015-07-24 2016-09-13 Sandisk Technologies Llc Select gates with select gate dielectric first
US9613971B2 (en) 2015-07-24 2017-04-04 Sandisk Technologies Llc Select gates with central open areas
CN108630807B (zh) * 2017-03-23 2022-01-28 中芯国际集成电路制造(上海)有限公司 半导体器件、制造方法以及存储器
KR102396583B1 (ko) * 2017-11-09 2022-05-11 삼성전자주식회사 메모리 소자 및 이의 제조방법
CN114695370B (zh) * 2022-05-31 2023-03-24 广州粤芯半导体技术有限公司 半导体结构及其制备方法
CN115881798A (zh) * 2023-01-29 2023-03-31 合肥新晶集成电路有限公司 半导体结构及其制备方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2683078A1 (fr) * 1991-10-29 1993-04-30 Samsung Electronics Co Ltd Memoire morte a masque de type non-et.
JP3184045B2 (ja) * 1994-06-17 2001-07-09 株式会社東芝 不揮発性半導体メモリ
JPH1065028A (ja) * 1996-08-23 1998-03-06 Toshiba Corp 不揮発性半導体記憶装置及びその製造方法
JPH10154802A (ja) * 1996-11-22 1998-06-09 Toshiba Corp 不揮発性半導体記憶装置の製造方法
KR19990015794A (ko) 1997-08-09 1999-03-05 윤종용 불휘발성 메모리 장치 및 그 제조 방법
JP2001044395A (ja) * 1999-08-04 2001-02-16 Nec Corp 不揮発性半導体記憶装置およびその製造方法
JP2001148428A (ja) * 1999-11-18 2001-05-29 Toshiba Microelectronics Corp 半導体装置
JP2003046062A (ja) * 2001-07-30 2003-02-14 Toshiba Corp 半導体メモリ装置の製造方法
JP4605956B2 (ja) * 2001-09-19 2011-01-05 株式会社リコー 半導体装置の製造方法
KR100437453B1 (ko) * 2002-05-23 2004-06-23 삼성전자주식회사 소노스 게이트 구조를 갖는 낸드형 비휘발성 메모리 소자및 그 제조방법
EP1671367A1 (en) * 2003-09-30 2006-06-21 Koninklijke Philips Electronics N.V. 2-transistor memory cell and method for manufacturing
US6996011B2 (en) * 2004-05-26 2006-02-07 Macronix International Co., Ltd. NAND-type non-volatile memory cell and method for operating same
JP2005123524A (ja) * 2003-10-20 2005-05-12 Toshiba Corp 半導体装置及びその製造方法
US6992929B2 (en) * 2004-03-17 2006-01-31 Actrans System Incorporation, Usa Self-aligned split-gate NAND flash memory and fabrication process
KR100559714B1 (ko) * 2004-04-19 2006-03-10 주식회사 하이닉스반도체 낸드 플래시 메모리 소자 및 이의 프로그램 방법
KR100697286B1 (ko) * 2005-05-31 2007-03-20 삼성전자주식회사 비휘발성 메모리 장치 및 그 형성 방법
KR100614802B1 (ko) * 2005-07-04 2006-08-22 삼성전자주식회사 불휘발성 메모리 장치의 셀 게이트 구조물 제조 방법
US7227786B1 (en) * 2005-07-05 2007-06-05 Mammen Thomas Location-specific NAND (LS NAND) memory technology and cells

Also Published As

Publication number Publication date
US7283393B2 (en) 2007-10-16
KR20070008901A (ko) 2007-01-18
CN1897283A (zh) 2007-01-17
CN100595925C (zh) 2010-03-24
JP2007027726A (ja) 2007-02-01
US20070012979A1 (en) 2007-01-18
KR101094840B1 (ko) 2011-12-16

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