JP5174435B2 - ウェットエッチングアンダカットを最小にし且つ超低ｋ（ｋ＜２．５）誘電体をポアシーリングする方法 - Google Patents

ウェットエッチングアンダカットを最小にし且つ超低ｋ（ｋ＜２．５）誘電体をポアシーリングする方法 Download PDF

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JP5174435B2
JP5174435B2 JP2007298307A JP2007298307A JP5174435B2 JP 5174435 B2 JP5174435 B2 JP 5174435B2 JP 2007298307 A JP2007298307 A JP 2007298307A JP 2007298307 A JP2007298307 A JP 2007298307A JP 5174435 B2 JP5174435 B2 JP 5174435B2
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layer
oxygen
precursor
film
silicon
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JP2008147644A5 (enrdf_load_stackoverflow
JP2008147644A (ja
Inventor
シュウ フイウェン
シェク メイ−イー
シャ リ−クン
アル−ヴァヤティ アミール
ウィッティー デレク
ムサード ハイチェム
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Applied Materials Inc
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Applied Materials Inc
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Priority claimed from US11/694,856 external-priority patent/US20070287301A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02052—Wet cleaning only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Inorganic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Physical Vapour Deposition (AREA)
JP2007298307A 2006-11-21 2007-11-16 ウェットエッチングアンダカットを最小にし且つ超低ｋ（ｋ＜２．５）誘電体をポアシーリングする方法 Active JP5174435B2 (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US86677006P 2006-11-21 2006-11-21
US60/866,770 2006-11-21
US11/694,856 US20070287301A1 (en) 2006-03-31 2007-03-30 Method to minimize wet etch undercuts and provide pore sealing of extreme low k (k<2.5) dielectrics
US11/694,856 2007-03-30

Publications (3)

Publication Number Publication Date
JP2008147644A JP2008147644A (ja) 2008-06-26
JP2008147644A5 JP2008147644A5 (enrdf_load_stackoverflow) 2010-12-02
JP5174435B2 true JP5174435B2 (ja) 2013-04-03

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JP2007298307A Active JP5174435B2 (ja) 2006-11-21 2007-11-16 ウェットエッチングアンダカットを最小にし且つ超低ｋ（ｋ＜２．５）誘電体をポアシーリングする方法

Country Status (4)

Country Link
JP (1) JP5174435B2 (enrdf_load_stackoverflow)
KR (1) KR100939593B1 (enrdf_load_stackoverflow)
CN (1) CN100550318C (enrdf_load_stackoverflow)
TW (1) TWI392024B (enrdf_load_stackoverflow)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8236684B2 (en) * 2008-06-27 2012-08-07 Applied Materials, Inc. Prevention and reduction of solvent and solution penetration into porous dielectrics using a thin barrier layer
CN101740332B (zh) * 2008-11-13 2012-04-25 中芯国际集成电路制造(北京)有限公司 一种半导体元件的蚀刻方法
US20120122320A1 (en) * 2010-11-17 2012-05-17 Applied Materials, Inc. Method Of Processing Low K Dielectric Films
US9034770B2 (en) * 2012-09-17 2015-05-19 Applied Materials, Inc. Differential silicon oxide etch
CN103839871B (zh) * 2012-11-21 2017-09-08 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法
CN105448705B (zh) * 2014-06-18 2018-05-04 无锡华润上华科技有限公司 一种消除晶圆氧化膜上微粒的方法及其氧化膜
CN105244257B (zh) * 2014-07-08 2020-06-23 中芯国际集成电路制造(上海)有限公司 改善多孔低k薄膜的突起缺陷的方法
CN105702619A (zh) * 2014-11-27 2016-06-22 中芯国际集成电路制造(上海)有限公司 半导体结构的形成方法
US20160225652A1 (en) 2015-02-03 2016-08-04 Applied Materials, Inc. Low temperature chuck for plasma processing systems
CN111863610A (zh) * 2020-05-12 2020-10-30 中国电子科技集团公司第十一研究所 一种制备电极孔的方法及计算机可读存储介质
CN113667976A (zh) * 2021-08-27 2021-11-19 中国科学院兰州化学物理研究所 一种具有封孔顶层的耐蚀dlc薄膜及其制备方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001077196A (ja) * 1999-09-08 2001-03-23 Sony Corp 半導体装置の製造方法
TW535253B (en) * 2000-09-08 2003-06-01 Applied Materials Inc Plasma treatment of silicon carbide films
US6890850B2 (en) * 2001-12-14 2005-05-10 Applied Materials, Inc. Method of depositing dielectric materials in damascene applications
US6936551B2 (en) * 2002-05-08 2005-08-30 Applied Materials Inc. Methods and apparatus for E-beam treatment used to fabricate integrated circuit devices
US6927178B2 (en) * 2002-07-11 2005-08-09 Applied Materials, Inc. Nitrogen-free dielectric anti-reflective coating and hardmask
US7005390B2 (en) * 2002-10-09 2006-02-28 Intel Corporation Replenishment of surface carbon and surface passivation of low-k porous silicon-based dielectric materials
KR100909175B1 (ko) * 2002-12-27 2009-07-22 매그나칩 반도체 유한회사 듀얼 다마신 패턴 형성 방법
KR100573484B1 (ko) * 2003-06-30 2006-04-24 에스티마이크로일렉트로닉스 엔.브이. 반도체 소자 및 그 제조 방법
KR20050014231A (ko) * 2003-07-30 2005-02-07 매그나칩 반도체 유한회사 반도체소자의 형성방법
JP2005050954A (ja) * 2003-07-31 2005-02-24 Toshiba Corp 半導体装置およびその製造方法
US20050037153A1 (en) * 2003-08-14 2005-02-17 Applied Materials, Inc. Stress reduction of sioc low k films
JP4015976B2 (ja) * 2003-08-28 2007-11-28 株式会社東芝 電子装置の製造方法
JP2005203568A (ja) * 2004-01-15 2005-07-28 Semiconductor Leading Edge Technologies Inc 半導体装置の製造方法及び半導体装置
JP2006332408A (ja) * 2005-05-27 2006-12-07 Sony Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
TWI392024B (zh) 2013-04-01
CN101202227A (zh) 2008-06-18
KR100939593B1 (ko) 2010-02-01
KR20080046087A (ko) 2008-05-26
JP2008147644A (ja) 2008-06-26
TW200826196A (en) 2008-06-16
CN100550318C (zh) 2009-10-14

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