TW200826196A - Method to minimize wet etch undercuts and provide pore sealing of extreme low K (K < 2.5) dielectrics - Google Patents

Method to minimize wet etch undercuts and provide pore sealing of extreme low K (K < 2.5) dielectrics Download PDF

Info

Publication number
TW200826196A
TW200826196A TW096140628A TW96140628A TW200826196A TW 200826196 A TW200826196 A TW 200826196A TW 096140628 A TW096140628 A TW 096140628A TW 96140628 A TW96140628 A TW 96140628A TW 200826196 A TW200826196 A TW 200826196A
Authority
TW
Taiwan
Prior art keywords
layer
film
oxygen
carbon
rich
Prior art date
Application number
TW096140628A
Other languages
Chinese (zh)
Other versions
TWI392024B (en
Inventor
hui-wen Xu
Meiyee Shek
Li-Qun Xia
Amir Al-Bayati
Derek R Witty
Saad Hichem M
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/694,856 external-priority patent/US20070287301A1/en
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Publication of TW200826196A publication Critical patent/TW200826196A/en
Application granted granted Critical
Publication of TWI392024B publication Critical patent/TWI392024B/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02043Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02052Wet cleaning only
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Plasma & Fusion (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Physical Vapour Deposition (AREA)

Abstract

Methods of processing films on substrates are provided. In one aspect, the methods comprise treating a patterned low dielectric constant film after a photoresist is removed from the film by depositing a thin layer comprising silicon, carbon, and optionally oxygen and/or nitrogen on the film. The thin layer provides a carbon-rich, hydrophobic surface for the patterned low dielectric constant film. The thin layer also protects the low dielectric constant film from subsequent wet cleaning processes and penetration by precursors for layers that are subsequently deposited on the low dielectric constant film.

Description

200826196 九、發明說明: 【發明所屬之技術領域】 本發明的各實施方式主要關於積體電路的製造。更具 體地說,本發明的各實施方式關於一種用於在低介電常數 層上沉積包含矽、碳,以及選擇性的包括氧和/或氮的薄層 的製程。 【先前技術】 自從幾十年前首次發明積體電路元件以來,積體電路 幾何構型的尺寸已經顯著地縮小。自從那時起,積體電路 一般都遵循著兩年尺寸減半的規則(通常稱爲摩爾法則), 這就意味著在晶片上的元件的數量每兩年增加一倍。目前 的製造設備常規可生産具有〇·13μπι甚至0·1μιη特徵尺寸 的元件,未來的設備將很快就能生産具有甚至更小特徵尺 寸的元件。 對元件幾何構型的不斷縮小産生了對具有更低介電常 數(k )值的夾層的需要,因爲必須降低相鄰金屬線之間的 電容耦合以進一步減小積體電路上元件的尺寸。特別是需 要具有低介電常數的絕緣體,其介電常數小於大約4 · 0。 近來,已開發出介電常數小於大約3.0的低介電常數 有機矽薄膜。還開發了介電常數小於2.5的極低k( extreme low k,ELK)有機矽薄膜。一種用於形成低介電常數和極 低介電常數有機矽薄膜的方法已用來由一種包含有機矽化 合物以及一種如碳氫化合物的化合物(其包含遇熱不穩定 6 200826196 或易揮發的基團)的氣體混合物來沉積該薄 所沉積的薄膜進行後處理,以從所沉積的薄 不穩定或易揮發的基團(例如有機基團)。從 中去除遇熱不穩定或易揮發的基團會在薄膜 寸的孔洞或孔隙,這將降低該薄膜的介電常 空氣的介電常數約爲1。 去除光阻劑或底抗反射塗層(bottom coating,BARC )的灰化製程可從k值較低 碳,並使該薄膜表面氧化。在後續的濕式蝕 氧化的低k薄膜表面將被去除,並促成底七 和臨界尺寸(CD )損失。 低&quot;電常數薄膜的多孔性也可導致應用 的後續各層(例如BARC層或金屬間化合物 等等))的沉積的前驅物的滲透。阻障層前驅 電常數薄膜的擴散造成了元件中的漏電流。 因此’目前仍然需要一種處理低介電 法’其可以在後續的製程步驟中(例如濕式 如BARC層和阻障層的後續各層的沉積)將 害減至最小。 【發明内容】 本發明主要提供一種在腔室中在基材上 薄膜上沉積一薄共形封孔表面層的方法。此 已圖案化的低介電常數薄膜上去除光阻劑, 膜,然後,對 膜中去除遇熱 已沉積的薄膜 中引起奈米尺 數,這是因爲 anti-reflective 的薄膜中脫出 刻製程中,經 7 (undercut) 於在該薄膜上 阻障層(TaN, 物向多孔低介 常數薄膜的方 製程,以及例 對於薄膜的損 的低介電常數 方法包括:從 並隨後通過沉 7 200826196 積一具有已控制的厚度在約4人到大約1 00A之間的薄共形 層來處理具有任何深寬比(aspect ratio )或介層洞(via ) 尺寸的已圖案化低介電常數薄膜,所述共形層在已圖案化 的低介電常數薄膜的表面上包含矽及碳並選擇性地包含氧 和/或氮。在一種實施方式中,該層的沉積包括在低RF功 率級別的存在下使八甲基環四矽氧烷起反應。光阻劑的灰 化製程從低介電常數薄膜的表面中脫碳,而且其表面變爲 &gt; 親水性的。在灰化後,封孔層表面恢復了低介電常數薄膜 的表面碳濃度,並爲已圖案化的低介電常數薄膜提供了一 個疏水表面。當低介電常數薄膜的表面疏水時,低介電常 數薄膜的濕式蝕刻速率是最小的。該層可以在後續可能在 基材上執行的濕式清洗製程中保護低介電常數薄膜,並防 止底切和CD損失。該薄層所提供的疏水表面可防止濕氣 被吸收進入低介電常數薄膜中。 在光阻劑灰化後,低介電常數薄膜表面變得氧化並包 括氫氧(0H )基。該表面吸收濕氣,而且極大地增加了其 I / 介電常數。光阻劑灰化後的薄層沉積驅出了吸收在表面中 的濕氣,並去除了在低介電常數薄膜表面的0H基,並從 而恢復了低介電常數。該薄層的沉積提供了能防止進一步 ' 濕氣吸收的一疏水密封層。 . 薄共形層可沉積在表面包含0H、NH或NH2基的任何 覆層或已圖案化薄膜上(包括表面具有氧化物(例如 Cu/CuO或A1/A1203)的介電質薄膜以及金屬薄膜),以作爲 一保護層以防止濕氣附著和濕式化學蝕刻,或作爲一封孔 8 200826196 層以防止前驅物或化學物質的穿透。該薄層也可作爲封孔 層用於表面具有OH、NH或NH2基的多孔介電質薄膜或金 屬薄膜。 【實施方式】200826196 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION Embodiments of the present invention mainly relate to the manufacture of an integrated circuit. More specifically, embodiments of the present invention relate to a process for depositing a thin layer comprising germanium, carbon, and optionally oxygen and/or nitrogen on a low dielectric constant layer. [Prior Art] Since the first invented integrated circuit components decades ago, the size of the integrated circuit geometry has been significantly reduced. Since then, integrated circuits have generally followed the two-year halving rule (often called the Moore rule), which means that the number of components on a wafer doubles every two years. Current manufacturing equipment routinely produces components with feature sizes of 〇·13μπι or even 0·1μηη, and future devices will soon be able to produce components with even smaller feature sizes. The ever-decreasing geometry of the components creates a need for an interlayer with a lower dielectric constant (k) value because the capacitive coupling between adjacent metal lines must be reduced to further reduce the size of the components on the integrated circuit. In particular, an insulator having a low dielectric constant is required, which has a dielectric constant of less than about 4.0. Recently, low dielectric constant organic germanium films having a dielectric constant of less than about 3.0 have been developed. An extremely low k (elt low k, ELK) organic germanium film having a dielectric constant of less than 2.5 has also been developed. A method for forming a low dielectric constant and very low dielectric constant organic germanium film has been used for a compound comprising an organic germanium compound and a hydrocarbon such as a hydrocarbon containing heat unstable 6 200826196 or a volatile group The gas mixture of the group is deposited to deposit the thin deposited film for post-treatment from the deposited thin unstable or volatile groups (e.g., organic groups). Removal of thermally unstable or volatile groups from the pores or pores in the film will reduce the dielectric constant of the film to about 1 for the dielectric constant air. The ashing process to remove the photoresist or bottom coating (BARC) can result in a lower k-value carbon and oxidation of the surface of the film. The surface of the subsequent wet etched low-k film will be removed and contribute to bottom seven and critical dimension (CD) losses. The porosity of the low &quot;electroconstant film can also result in the penetration of precursors deposited by subsequent layers of the application (e.g., BARC layers or intermetallic compounds, etc.). The diffusion of the barrier precursor precursor constant film causes leakage current in the device. Thus, there is still a need for a low dielectric process that can minimize damage during subsequent processing steps, such as deposition of wet layers such as BARC layers and subsequent layers of barrier layers. SUMMARY OF THE INVENTION The present invention generally provides a method of depositing a thin conformal sealing surface layer on a film on a substrate in a chamber. The patterned low dielectric constant film removes the photoresist, the film, and then removes the heat-deposited film in the film to cause nanometer scale, because the anti-reflective film is removed from the engraving process. Medium, undercut (undercut) on the film (TaN, the process of the porous low-k dielectric film, and the low dielectric constant method for the loss of the film include: from and then through the sink 7 200826196 A patterned conformal low dielectric constant film having any aspect ratio or via size is processed by a thin conformal layer having a controlled thickness between about 4 and about 100 A. The conformal layer comprises germanium and carbon on the surface of the patterned low dielectric constant film and optionally oxygen and/or nitrogen. In one embodiment, the deposition of the layer is included at a low RF power level In the presence of octamethylcyclotetraoxane, the ashing process of the photoresist is decarburized from the surface of the low dielectric constant film, and the surface thereof becomes &gt; hydrophilic. After ashing, The surface of the sealing layer is restored to a low dielectric constant The surface carbon concentration of the film provides a hydrophobic surface for the patterned low dielectric constant film. When the surface of the low dielectric constant film is hydrophobic, the wet etching rate of the low dielectric constant film is minimal. The low dielectric constant film can be protected and the undercut and CD loss can be prevented in a subsequent wet cleaning process that may be performed on the substrate. The thin layer provides a hydrophobic surface that prevents moisture from being absorbed into the low dielectric constant film. After the photoresist is ashed, the surface of the low dielectric constant film becomes oxidized and includes hydrogen hydroxide (OH). The surface absorbs moisture and greatly increases its I / dielectric constant. The thin layer deposition removes the moisture absorbed in the surface and removes the 0H radical on the surface of the low dielectric constant film, thereby restoring the low dielectric constant. The deposition of the thin layer provides protection against further A hydrophobic seal layer for moisture absorption. A thin conformal layer can be deposited on any coating or patterned film containing 0H, NH or NH2 groups on the surface (including oxides on the surface (eg Cu/CuO or A1/) Dielectric of A1203) Thin film and metal film) as a protective layer to prevent moisture adhesion and wet chemical etching, or as a hole 8 200826196 layer to prevent the penetration of precursors or chemicals. The thin layer can also be used as a sealing hole The layer is used for a porous dielectric film or a metal film having an OH, NH or NH2 group on the surface.

本發明的實施方式提供了 一種在已圖案化的基材上沉 積包含矽、碳,以及選擇性的包括氧和/或氮的薄共形層的 方法。在一方面,本發明的實施方式提供一種用於圖案化 低介電常數薄膜的光阻劑從該薄膜上去除後,保護已圖案 化的低介電常數薄膜的方法。在另外一些方面,本發明的 實施方式提供了一種控制内連線(innterconnect )中金屬 線的臨界尺寸,和一種將沉積層的厚度控制在大約4A到 大約100人之間的方法。 在一種實施方式中,應用光阻劑以及光微影技術在基 材上圖案化一低介電常數薄膜,以在其中形成一垂直内連 線孔或一水平内連線孔。所述低介電常數薄膜可以是一種 包含石夕、碳,並選擇性地包含氧和/或氣的薄膜。所述低介 電常數薄膜可由一種包含有機矽化合物(諸如有機矽烷或 有機矽氧烷)的氣體混合物沉積。氣體混合物也可以包括 一種氧化氣體。在一種實施方式中,所述氣體混合物包括 一種有機碎化合物和一種成孔劑,例如碳氫化合物,其在 該薄膜沉積之後從該薄膜上去除,以在該薄膜中造成孔洞 或孔隙並降低該薄膜的介電常數。所述成孔劑可通過UV (紫外線)處理、電子束處理、熱處理或其組合來去除。 9 200826196 形成多孔低介電常數薄膜的方法在共同受讓的美國專利號 6 9 3 6 5 5 1以及美國專利號7 0 6 0 3 3 0中得到進一步的詳細描 述,在這裏引用參考。應該注意的是,具有其他組成和/ 或由不同氣體混合物沉積的低介電常數薄膜可應用於本發 明的實施方式中。 也值得注意的是,除低介電常數薄膜外的其他薄膜也 可應用於實施方式中,例如表面包含〇H,NH或NH2基的 任何薄膜。概括而言,可應用的薄膜具有富氧或富氮表面, . 這一表面可選擇性地沉積一種其上包含矽、碳並選擇性地 包含氧和/或氮的薄膜。如這裏的定義,富氧表面的Si:〇(矽: 氧)比例在大約1 : 1到大約1 : 3之間。如這裏的定義,富氮 表面的Sl:N(矽:氮)比例在大約1 :1到大約1 :2之間。 雖然可將薄膜沉積在富氧或富氮表面上,該薄膜一般 不會在富碳表面上生長,並因而,該薄膜在富氧或富氮表 面上的沉積可以被描述爲選擇性沉積製程。 八甲基環四石夕氧烧(octamethylcyclotetrasiloxane, (J 0MCTS)是可應用於沉積在此描述的薄層的前驅物的一個 例子。除八甲基環四矽氧烷外,通式爲Rx-Si-(〇R,)y的前 驅物也犯被用於以適當的製程窗口 ( pr〇cess wincj〇w)來 &gt;儿積薄共形層,例如二甲基二甲氧基矽燒 • (CH3)2-Si-(〇_CH3)2,其中每個 R = H、CH3、CH2CH3 或其 他统基’每個r,= CH3、CHzCH3或其他烷基,X的取值範 圍爲〇到4,y的取值範圍爲〇到4,同時x + y = 4。其他可 採用的前驅物包括結構爲(Rx-si-0-Si-Ry)z的有機二矽氣 10 200826196 院,例如1 ’ 3-二甲基二矽氧烷(cHs-SiHyO-SiHyCHs)、1, 1,3,3 — 、四甲基二矽氧烷((CH3)2-SiH-0-SiH-(CH3)2)、六 甲基二^ _ 土 氣燒((CH3)3-Si-〇-Si-(CH3)3)等。其他可應用的前 驅物包括产+ 长有機矽氧烷(Rx-Si-〇)y,其中y的值大於2,X 的取值範圍g _爲1到2,以及rx = ch3、CH2CH3或其他烷基。 可應用@ ^ 、I有機矽化合物包括具有3個或更多矽原子的環 狀衾士摄, 、 以及%狀結構進一步包括一個或更多氧原子的環 ΟEmbodiments of the present invention provide a method of depositing a thin conformal layer comprising tantalum, carbon, and optionally oxygen and/or nitrogen on a patterned substrate. In one aspect, embodiments of the present invention provide a method for protecting a patterned low dielectric constant film after the photoresist for patterning a low dielectric constant film is removed from the film. In other aspects, embodiments of the present invention provide a method of controlling the critical dimension of a metal line in an innterconnect, and a method of controlling the thickness of the deposited layer between about 4A and about 100 people. In one embodiment, a low dielectric constant film is patterned on the substrate using a photoresist and photolithography to form a vertical interconnect or a horizontal interconnect. The low dielectric constant film may be a film comprising stone, carbon, and optionally oxygen and/or gas. The low dielectric constant film may be deposited from a gas mixture comprising an organic cerium compound such as an organic decane or an organic decane. The gas mixture may also include an oxidizing gas. In one embodiment, the gas mixture comprises an organic ground compound and a pore former, such as a hydrocarbon, which is removed from the film after deposition of the film to create voids or voids in the film and to reduce the The dielectric constant of the film. The pore former may be removed by UV (ultraviolet) treatment, electron beam treatment, heat treatment, or a combination thereof. 9 200826196 A method of forming a porous low dielectric constant film is further described in detail in commonly assigned U.S. Patent No. 6,93,651, and U.S. Patent No. 7,060,036, incorporated herein by reference. It should be noted that low dielectric constant films having other compositions and/or deposited from different gas mixtures can be employed in embodiments of the present invention. It is also worth noting that other films than low dielectric constant films can be used in embodiments such as any film having a surface comprising 〇H, NH or NH2 groups. In summary, the applicable film has an oxygen-rich or nitrogen-rich surface. This surface selectively deposits a film comprising ruthenium, carbon and optionally oxygen and/or nitrogen thereon. As defined herein, the oxygen-rich surface has a Si: 矽 (矽: oxygen) ratio of between about 1:1 and about 1:3. As defined herein, the ratio of Sl:N (矽:nitrogen) of the nitrogen-rich surface is between about 1:1 and about 1:2. While the film can be deposited on an oxygen-rich or nitrogen-rich surface, the film generally does not grow on the carbon-rich surface, and thus, the deposition of the film on the oxygen-rich or nitrogen-rich surface can be described as a selective deposition process. Octamethylcyclotetrasiloxane (J 0MCTS) is an example of a precursor that can be applied to the deposition of the thin layers described herein. In addition to octamethylcyclotetraoxane, the formula is Rx- The precursor of Si-(〇R,)y is also used to form a conformal layer, such as dimethyldimethoxy oxime, in a suitable process window (pr〇cess wincj〇w). (CH3)2-Si-(〇_CH3)2, where each R = H, CH3, CH2CH3 or other radical 'each r, = CH3, CHzCH3 or other alkyl, X has a range of values 4, y ranges from 〇 to 4, while x + y = 4. Other precursors that can be used include organic diterpene 10 with a structure of (Rx-si-0-Si-Ry)z 200826196, for example 1 '3-Dimethyldioxane (cHs-SiHyO-SiHyCHs), 1,1,3,3 -, tetramethyldioxane ((CH3)2-SiH-0-SiH-(CH3) 2), hexamethyldi^ _ rustic burning ((CH3)3-Si-〇-Si-(CH3)3), etc. Other applicable precursors include production + long organic decane (Rx-Si-〇) y, where the value of y is greater than 2, the range of values of X g _ is 1 to 2, and rx = ch3, CH2CH3 or other Group may be applied @ ^, I comprises an organic silicon compound having cyclic quilt Axis cameras 3 or more silicon atoms, and the structure further comprises a% or more ring oxygen atom Ο

狀会士構 〇 市售可購得的環有機矽化合物包括具有交替的矽 和氧原子’和一個或兩個烷基與矽原子結合的環。例如, 壞有機石夕化合物可以包括一個或更多以下的化合物: 六甲基環三矽氧烷 (-Si(CH3)2-0)3-環, 1 ’ 3 ’ 5,7-四曱基環四石夕氧烧(TMCTS) (-SiH(CH3)2-0如環, 八曱基環四矽氧烷(OMCTS) (-Si(CH3)2-0-)4-環,以及 卜3,5,7,9-五甲基環五矽氧烷 (-SiH(CH3)-0-)5-環。 所述薄層包含矽、碳,並選擇性地包含氧。在另一種 實施方式中,前驅物可爲含矽和含氮前驅物,其用於沉積 包含矽、氮並選擇性地包含碳的薄共形層。前驅物可包括 直鏈型矽氮烷和環型矽氮烷。直鏈型矽氮烷可包括 R-Si-NH-Si-R’結構,其中R = CH3、CH2CH3或其他烷基, R’=H、CH3、CH2CH3或其他烷基。環型矽氮烷可包括 (Rx-Si-NH)Y結構,其中y的值大於2,x的取值範圍爲從 1到2,以及RX = CH3、CH2CH3或其他烷基。環型矽氮烷化 合物可包括具有三個或更多矽原子的環狀結構,並且環狀 結構進一步包括一個或更多氮離子。市售可購得的環型矽 11The cyclic organic oxime compound commercially available has a ring having alternating oxime and oxygen atoms' and one or two alkyl groups bonded to a ruthenium atom. For example, a bad organic compound can include one or more of the following compounds: hexamethylcyclotrioxane (-Si(CH3)2-0)3-ring, 1 '3' 5,7-tetradecyl环四石夕氧烧(TMCTS) (-SiH(CH3)2-0 such as ring, octadecylcyclotetraoxane (OMCTS) (-Si(CH3)2-0-) 4-ring, and 5,7,9-pentamethylcyclopentaoxane (-SiH(CH3)-0-) 5-ring. The thin layer comprises ruthenium, carbon, and optionally oxygen. In another embodiment The precursor may be a cerium-containing and nitrogen-containing precursor for depositing a thin conformal layer comprising cerium, nitrogen, and optionally carbon. The precursor may include a linear decazane and a cyclic decazane. The linear decazane may comprise an R-Si-NH-Si-R' structure wherein R = CH3, CH2CH3 or other alkyl group, R' = H, CH3, CH2CH3 or other alkyl group. The (Rx-Si-NH)Y structure may be included, wherein the value of y is greater than 2, the value of x ranges from 1 to 2, and RX = CH3, CH2CH3 or other alkyl groups. The cyclic decazane compound may include a ring structure of three or more germanium atoms, and the ring structure further includes one or more Nitrogen ion. Commercially available ring type 矽 11

200826196 氮院化合物包括具有交替的碎和氛原子,和一個或 基與矽原子結合的環。例如,環型矽氮烷化合物可 以下物質: 1,2,3,4,5,6,7,8-八甲基環四石夕氣院, 1,2,3,4,5,6-六甲基環三石夕氮烧, 卜;1,3,3,5,5-六甲基環三矽氮烷,以及 1,1,3,3,5,5,7,7-八甲基環四碎氮烧。 第1A圖示出了在基材100上低介電常數薄膜 一個例子。第1 B圖示出了在低介電常數薄膜1 02 圖案化的光阻劑104。 隨後通過例如去光阻或灰化處理從低介電常數 除去光阻劑。第1C圖示出了通過光阻劑1 04圖案 成内連線 1 06以及光阻劑被去除後的低介電常 102。薄共形層108 (即厚度爲大約4A至約100A 該層包括石夕、碳並選擇性地包括氧和/或氮,隨後沉 圖案化的低介電常數薄膜表面,如第1 D圖所示。名 率存在的條件下,該層可通使一種氣體混合物(例 包含矽、氧,以及碳的氣體混合物)反應來沉積。石j 和碳元素是由有機石夕化合物來提供,例如八曱基環 烷。有機矽化合物典型情況下是和載氣注入腔室的 地,載氣爲氦氣。但是也可應用其他惰性氣體,例 或氮氣。 在該層沉積之後,將對基材進行濕式清洗,例 1 00: 1 HF溶液。隨後,如第1 E圖所示,層1 1 0,例 兩個烧 以包括200826196 Nitrogen compound includes a ring having alternating cleavage and ambience atoms, and one or a group bonded to a ruthenium atom. For example, a cyclic decazane compound can be used as a substance: 1,2,3,4,5,6,7,8-octamethylcyclotetrazet, 1,2,3,4,5,6- Hexamethylcyclotrifluoride, abbreviated; 1,3,3,5,5-hexamethylcyclotriazane, and 1,1,3,3,5,5,7,7-octamethyl The ring is broken with nitrogen. Fig. 1A shows an example of a low dielectric constant film on a substrate 100. FIG. 1B shows the photoresist 104 patterned in the low dielectric constant film 102. The photoresist is then removed from the low dielectric constant by, for example, photoresist removal or ashing. Fig. 1C shows the low dielectric constant 102 after the photoresist 106 is patterned into the interconnect 106 and the photoresist is removed. Thin conformal layer 108 (ie, having a thickness of from about 4 A to about 100 A. The layer comprises a stone, carbon, and optionally oxygen and/or nitrogen, followed by a patterned low dielectric constant film surface, as shown in FIG. In the presence of a nominal rate, the layer may be deposited by reacting a gas mixture (such as a gas mixture comprising helium, oxygen, and carbon). The stone j and carbon are provided by an organic stone compound, such as eight. Indolyl naphthenes. Organic ruthenium compounds are typically injected into the chamber with a carrier gas. The carrier gas is helium. However, other inert gases, such as nitrogen, may also be used. After deposition of the layer, the substrate will be applied. Wet cleaning, Example 1 00: 1 HF solution. Subsequently, as shown in Figure 1 E, layer 1 10, for example, two burns to include

102的 上的已 薄膜上 化以形 數薄膜 的層) 積在已 :RF功 如一種 &gt;、氧, 四矽氧 。較佳 如氬氣 如應用 如PVD 12 200826196 阻障層或ALD阻障層(例如ALD氮化钽(TaN)層)可以沉 積在該層上。作爲另一種選擇,如第1F圖所示,一層, 例如阻障抗反射塗層(BARC)的層120,可以沉積在層108 上並填充内連線106。 在RF功率存在的情況下,在化學氣相沉積腔室或電 漿增強化學氣相沉積腔室中,可以通過使一種包含有機石夕 化合物的氣體混合物起反應,來沉積包括矽、碳並選擇性 地包括氧和/或氮的層。可用於沉積該層的腔室的實例包 括:具有兩個隔離的處理區域的 PRODUCER®腔室以及 DxZ®腔室,這兩種腔室都可以從Santa Clara,California 的Applied Materials’Inc·(美國加州的聖大克勞拉市的應 用材料公司)市售購得。在此提供的製程條件是爲具有兩 個隔離處理區域的 3 00mm PRODUCER⑧腔室而提供。因 而’母個基材處理區域和每個基材的流速是腔室中的流速 的一半。 典型情況下,腔室中,在所述層沉積於基材上的過程 (J 中,將基材的溫度維持在大約150°C至約4〇〇〇c之間。用 於3 00mm基材提供的RF功率的功率值爲大約i〇〇w或更 低,例如在大約30W至約75W之間。一般而言,RF功率 &quot; 可以大約〇.l〇9W/cm2或更低來提供,例如在大約 . 〇.〇33W/cm2到約0.082W/cm2之間。RF功率可以提供到喷 頭(shower head ),例如氣體分配組件,和/或腔室的基材 支架。以大約13MHz至14MHz之間的高頻率提供RF功 率’較佳的情況下爲13·56ΜΗζ。RF功率可爲週期的或脈 13 200826196 衝的° RF功率也可爲連續的或不連續的。喷頭和基材支架 之間的間隔大於約 200mil,例如在大約 200mil至約 1400mil之間。腔室中的壓力爲大約1 .5Torr或更高,例如 在大約1.5T〇rr至約8Torr之間。 有機石夕化合物可以大約丨〇〇SCCm至約1 OOOsccm之間 的流速注入該腔室。載氣將以大約lOOsccm至約70〇〇sccm Ο Ο 之間的流速注入該腔室。在腔室中,有機矽化合物(例如 八甲基環四石夕氧烷(〇MCTS,sccm))的流速與載氣(例如 氮氣(seem))的流速注入腔室之比爲大約〇1或更高。根 據已圖案化的基材的深寬比,該層可以沉積-段時間,諸 如時間範圍在(M秒到600 f少之間,以沉積厚度在約Μ 至約1 00人之間的層。典型情況下,當應用更高深寬比時, 該層的’儿積需要更長的時間以提供共形表面。 物作爲前驅物時,可 100A之間的薄、均勻 已經獲得了在單個 如在此所定義,‘‘自 的前驅物,例如不考 物的。厚度可通過前 前驅物具有不同的分 層的不同厚度。該薄 條件下,薄層的存在 一般而言, 飽和 x現’應用上述的RF功率 流速比,當應用一自飽和有機矽化合 以可靠地沉積厚度僅在大約4A至約 的共形層。應用在此提供的條件, 300mm基材中厚度範圍爲u的層。 飽和前驅物”是在基材上沉積一薄層 慮沉積時間長度下僅一分子層的前驅 驅物的選擇來控制,這是由於不同的 子尺寸,導致不同前驅物的一個分子 層的存在,在用於沉積該薄層的製程 阻礙了從前驅物進一步沉積爲附加層 14 200826196 前驅物可以包括甲基,以抑制該薄層繼續生長。〇MCTS 是一較佳的自飽和前驅物’這是由於其包含大量甲基基 團,這些甲基導致一層的自飽和沉積,因爲曱基基團中的 碳提供充分抑制在其上進一步沉積的富碳薄膜表面。也即 是說,一旦下方基材的表面由OMCTS分子覆蓋,可以由 0MCTS沉積共形第一層,在所沉積層表面的Si-CH3鍵的 存在提供了抑制進一步沉積的富碳表面,直至一些甲基基 團通過其他一些該層的處理去除。從而,就可很好地控制 • 0MCTS的每個分子層的沉積,這將提高最終層的臺階覆蓋 性(step coverage)。 除八曱基環四矽氧烷外,其他可用的前驅物包括二乙 氧基甲基矽烷(DEMS)、六甲基二矽氧烷(HMD0S),以及六 曱基二矽烷(HMDS)。其他包含Si、C及Η的前驅物可用 於本製程,例如三曱基矽烷、四甲基石夕烧等。 在未暴露於灰化製程的低介電常數薄膜上,並在暴露 於光阻劑灰化的低介電常數薄膜上執行X射線光電電譜 Ο (X-ray photoelectron spectroscopy,XPS)分析。在暴露於光 阻劑灰化並隨後在其上沉積一薄層來處理的低介電常數薄 膜上也執行XPS分析’其中根據本發明的實施方式,該薄 層由0MCTS沉積並包含矽、碳及氧。XPS分析顯示,將 - 薄層沉積在灰化的低介電常數薄膜上,與其上未通過沉積 薄膜來處理的低介電常數薄膜相比,可以在該些膜表面提 供更高的碳含量(原子數。/。碳)。例如,經灰化的低介電常數 薄膜可能具有大約3原子數%碳,而未經灰化的低介電常 15 200826196 數薄膜上的薄層在表面提供約1 5原子數%碳。因而,從一 方面說,薄層爲富碳層。該薄層的碳含量在大約5原子數 %碳至約3 0原子數%碳之間。灰化步驟係脫去了低介電常 數薄膜的表面的碳濃度,然而在灰化過的低介電常數薄膜 上沉積薄層恢復了表面碳濃度。 XPS分析也顯示了用薄層處理的低介電常數薄膜表面 的氧含量低於那些在灰化後沒有用該薄層處理的低介電常 數薄膜表面的氧含量,這是因爲已灰化薄膜表面的OH基 被含碳的薄層取代。用包含碳的薄層取代已灰化薄膜表面 的OH基也降低了已灰化薄膜的介電常數。第2圖示出了 在低介電常數薄膜上應用 OMCTS沉積薄層會降低經過三 個不同灰化製程中一個製程的薄膜的灰化後介電常數。The film on the upper surface of the film is formed by a layer of the film: RF work such as a &gt;, oxygen, tetrahydrogen. Preferably, an argon gas such as a PVD 12 200826196 barrier layer or an ALD barrier layer (e.g., an ALD tantalum nitride (TaN) layer) may be deposited on the layer. Alternatively, as shown in FIG. 1F, a layer, such as a barrier anti-reflective coating (BARC) layer 120, may be deposited on layer 108 and filled with interconnects 106. In the presence of RF power, in a chemical vapor deposition chamber or a plasma enhanced chemical vapor deposition chamber, deposition can be carried out by reacting a gas mixture containing an organic compound, including strontium, carbon, and A layer comprising oxygen and/or nitrogen is included. Examples of chambers that can be used to deposit this layer include: PRODUCER® chambers with two isolated processing areas and DxZ® chambers, both of which are available from Santa Clara, California's Applied Materials' Inc. (USA) Applied Materials, Inc. of Santa Clara, Calif., is commercially available. The process conditions provided herein are provided for a 300 mm PRODUCER 8 chamber with two isolated processing zones. Therefore, the flow rate of the parent substrate processing area and each substrate is half of the flow rate in the chamber. Typically, in the chamber, during the process of depositing the layer on the substrate (J, the temperature of the substrate is maintained between about 150 ° C and about 4 ° C. For a 300 mm substrate The power value of the supplied RF power is about i〇〇w or lower, for example between about 30 W and about 75 W. In general, the RF power can be provided at approximately 〇.l〇9 W/cm2 or lower, For example, between about 〇.〇33W/cm2 to about 0.082W/cm2. RF power can be supplied to a shower head, such as a gas distribution assembly, and/or a substrate holder for the chamber. The high frequency between 14MHz provides RF power 'better 13.56ΜΗζ. RF power can be periodic or pulse 13 200826196 rushed ° RF power can also be continuous or discontinuous. Head and substrate The spacing between the stents is greater than about 200 mils, such as between about 200 mils to about 1400 mils. The pressure in the chamber is about 1.5 Torr or higher, such as between about 1.5 T rr rr to about 8 Torr. The chamber can be injected at a flow rate between about SCCm and about 1 OOOsccm. The carrier gas will be approximately 10 A flow rate between Osccm and about 70 〇〇sccm Ο 注入 is injected into the chamber. In the chamber, the flow rate of the organic ruthenium compound (for example, octamethylcyclotetrazepine (〇MCTS, sccm)) and the carrier gas ( For example, the ratio of the flow rate of the injection chamber to the chamber is about 〇1 or higher. Depending on the aspect ratio of the patterned substrate, the layer can be deposited for a period of time, such as a time range of (M seconds to 600). Between f, to deposit a layer having a thickness between about Μ and about 100. Typically, when a higher aspect ratio is applied, the layer's product needs a longer time to provide a conformal surface. When the material acts as a precursor, a thin, uniform between 100A can be obtained in a single, as defined herein, ''self-precursor, such as no test. The thickness can be different through the pre-precursor. Different thicknesses. Under the thin condition, the presence of a thin layer is generally saturated, and the application of the above RF power flow rate ratio when applying a self-saturated organic germanium compound to reliably deposit a conformal thickness of only about 4A to about Layer. Apply the conditions provided here, thickness in 300mm substrate The layer of u. The saturated precursor is controlled by the choice of depositing a thin layer of precursor drive on the substrate for only one molecule layer over the length of deposition, due to the different sub-sizes that result in different precursors. The presence of a molecular layer, in the process for depositing the thin layer, hinders further deposition from the precursor to an additional layer. 14 200826196 The precursor may include a methyl group to inhibit the continued growth of the thin layer. 〇MCTS is a preferred self. Saturated Precursor 'This is because it contains a large number of methyl groups which cause a self-saturated deposition of one layer because the carbon in the thiol group provides sufficient inhibition of the surface of the carbon-rich film on which it is further deposited. That is, once the surface of the underlying substrate is covered by the OMCTS molecules, the conformal first layer can be deposited by the OCTS, and the presence of Si-CH3 bonds on the surface of the deposited layer provides a carbon-rich surface that inhibits further deposition until some The methyl group is removed by treatment of some other layer. Thus, the deposition of each molecular layer of the 0MCTS is well controlled, which will increase the step coverage of the final layer. In addition to the octadecylcyclotetraoxane, other useful precursors include diethoxymethyl decane (DEMS), hexamethyldioxane (HMDOS), and hexamethylene dioxane (HMDS). Other precursors containing Si, C and ruthenium may be used in the process, such as tridecyl decane, tetramethyl sulphate, and the like. X-ray photoelectron spectroscopy (XPS) analysis was performed on a low dielectric constant film that was not exposed to the ashing process and on a low dielectric constant film exposed to photoresist ashing. XPS analysis is also performed on a low dielectric constant film that is exposed to photoresist ashing and subsequent deposition of a thin layer thereon. [In accordance with an embodiment of the present invention, the thin layer is deposited by OCMC and contains germanium, carbon. And oxygen. XPS analysis showed that a thin layer was deposited on the ashed low dielectric constant film, which provided a higher carbon content on the surface of the film than the low dielectric constant film that was not processed by the deposited film ( The number of atoms. /. carbon). For example, an ashed low dielectric constant film may have about 3 atomic percent carbon, while a non-ashing low dielectric constant 15 200826196 thin film provides about 15 atomic percent carbon on the surface. Thus, in one aspect, the thin layer is a carbon rich layer. The thin layer has a carbon content of between about 5 atomic percent carbon and about 30 atomic percent carbon. The ashing step removes the carbon concentration of the surface of the low dielectric constant film, whereas depositing a thin layer on the ashed low dielectric constant film restores the surface carbon concentration. The XPS analysis also shows that the surface of the low dielectric constant film treated with the thin layer has a lower oxygen content than the surface of the low dielectric constant film which is not treated with the thin layer after ashing, because the ash film has been ashed. The OH group of the surface is replaced by a thin layer containing carbon. Replacing the OH groups of the surface of the ashed film with a thin layer containing carbon also reduces the dielectric constant of the ashed film. Figure 2 shows that the application of OMCTS to deposit a thin layer on a low dielectric constant film reduces the post-ashing dielectric constant of a film that has undergone one of three different ashing processes.

灰化前以及灰化後用於低介電常數薄膜的濕潤角(在 第3圖中分別爲ELK ILD(即極低k夾層介電質)及已灰化 的ELK ILD ),以及灰化後並且其上具有薄OMCTS層的低 介電常數薄膜也得到測量。其結果如第3圖所示。在第3 圖中,灰化後的低介電常數薄膜上沉積薄OMCTS層增加 了低介電常數薄膜的濕潤角。增加的濕潤角顯示了薄 OMCTS層增加了低介電常數薄膜表面的疏水性。這樣的疏 水性增加是所希望的,這是因爲疏水表面可防止濕氣吸附 在低介電常數薄膜中,其中這種吸附將影響薄膜性能或至 少導致需要加入一些用於去除濕氣的耗時步驟。 灰化後濕式清洗後,在内連線的剖面上沉積薄共形 OMCTS層的效果也得到了檢驗。在薄膜在濕式清洗製程中 16 200826196 /父/包在100.1 HF&gt;谷液中後,對具有或不具有薄omcts層 的低介電常數薄膜中溝渠密度高的區域和溝渠密度低的區 域的溝渠剖面進行檢驗。Wetting angle for low dielectric constant film before ashing and after ashing (ELK ILD (ie very low k interlayer dielectric) and ashed ELK ILD in Fig. 3), and after ashing And a low dielectric constant film having a thin OMCTS layer thereon was also measured. The result is shown in Fig. 3. In Figure 3, the deposition of a thin OMCTS layer on the ashed low dielectric constant film increases the wetting angle of the low dielectric constant film. The increased wetting angle shows that the thin OMCTS layer increases the hydrophobicity of the surface of the low dielectric constant film. Such an increase in hydrophobicity is desirable because the hydrophobic surface prevents moisture from adsorbing in the low dielectric constant film, where such adsorption will affect the film properties or at least cause the need to add some time for removing moisture. step. After wet cleaning after ashing, the effect of depositing a thin conformal OMCTS layer on the cross section of the interconnect was also examined. After the film is wet-cleaned in the process of 16200826196/parent/package in 100.1 HF&gt; trough, for areas with high trench density and low trench density in low dielectric constant films with or without thin omcts The trench profile is tested.

第4A-4C圖示出了溝渠密度高的區域的溝渠剖面。第 4A圖示出了灰化後和濕式清洗前的溝渠剖面。第4B和4C 圖示出了灰化後並在濕式清洗後,低介電常數薄膜在其上 分別不具有和具有薄OMCTS層的溝渠剖面。第4B圖示出 了對於不具有薄OMCTS層的低介電常數薄膜中的溝渠, 濕式清洗將引起大約30nm的臨界尺寸損失。第4C圖示出 了在濕式清洗前其上沉積薄OMCTS層的低介電常數薄膜 時’將不會觀察到這樣的CD損失。 第5A-5C圖示出了溝渠密度低的區域的溝渠剖面。第 5 A圖示出了灰化後和濕式清洗前的溝渠剖面。第$ b和$ c 圖示出了灰化後並在濕式清洗後,低介電常數薄膜在其上 分別不具有和具有 '薄0MCTS層的溝渠剖面。第5b圖:出 了對於在其上不具有薄0MCTS層的低介電常數薄膜中的 溝渠,濕式清洗將引起大於大約3〇ηιη的庙&amp; ^ J紙切。第5C圖示 出了在濕式清洗前其上沉積薄OMCTS層的把人&amp; i 屬的低介電常數薄 膜時’將不會觀察到這樣的底切。 因此’該薄OMCTS層提供了一個富排主 田石反表面,其進而 提供了-個用於防止低k值薄膜在濕式钱刻製程期間臨界 尺寸的損失及底切的疏水表面。 我們可以看出,根據本發明實施方式所提供的薄層, 充當了緻密的封孔層的角色,可用於阻止 曰 此一種材料(諸如 17 200826196 用作之後沉積BARC層的BARC,或用作之後沉積阻障層 的一種PVP卩旦障前驅物或一種ALD前驅物(例如ald 丁― 前驅物))滲透進入薄層沉積於其上的多孔低k值薄膜。 例如,在介層洞蝕刻以及介層洞第一鑲嵌(damaseene) 製程中的光阻劑灰化之後,該薄層可沉積在低介電常數薄 膜上。隨後的BARC填充可在該薄層上進行。該薄層提供 了用於防土 BARC材料滲透到介電質薄膜中的封孔層。然 後,在低介電常數薄膜與下面導體材料(諸如銅)之間的 介電質阻障物將被蝕刻,以使下面的導電材料在溝渠蝕刻 以及光阻劑移除後暴露出來。在蝕刻介電質阻障物之後, 可使用還原化學反應來清洗通過移除介電質阻障物所暴露 出來的導電表面’並且來從該表面移除氧化物(諸如氧化 銅(C u Ο))。該薄層接著被沉積在介層洞與溝渠的側壁上。 該薄層提供了一封孔層,其可以阻止之後阻障層前驅物滲 透進入低介電常數薄膜。 在濕式清洗基材之後將BARC層沉積在薄層上的實施 方式中,該薄層可用氦(或其他惰性氣體)電漿進行後處 理,以調整該薄層的表面的碳濃度和該薄層的濕潤角。該 濕潤角可降至約7〇。0或更小,以促進BARC層的濕潤和 沉積。第6圖示出了隨著電漿處理時間的增加會降低濕潤 角。使用溫和製程條件(例如,在大約3〇w至約l〇〇w之 間的R F功率’以及在大約1 〇 〇 s c c m至約1 〇 〇 〇 〇 s c c m之間 的He流速),以便電漿處理將不會破壞該薄層的封孔特性。 如果需要調整表面濕潤或接觸角,在除了 BARC層的 18 200826196 其他層(例如A L D阻障層)在薄層上沉積以前,也可 層進行氦電漿後處理。可應用不同氣體來電漿後處理 層,例如〇2、C〇2、N2〇、NH3、H2、氮、氮、氮或它 組合。電漿後處理可以改變該層表面的特性和性質, 表面張力和表面接觸角。 在另一種實施方式中,提供了一種控制内連線中 線的臨界尺寸的方法。如前面實施方式中所述,這種 包括在已圖案化的低介電常數薄膜上沉積薄層。在薄 積於已圖案化的低介電常數薄膜上之前,該已圖案化 介電常數薄膜可包含一個富氧或富氮表面。在該層 後,將用於沉積該層的前驅物(例如0 M C T S )的流動 終止,並僅通過向腔室中注入載氣(例如 He載氣) 何剩餘前驅物從腔室中清除。可將腔室淨化(purge ) 除(pump),或將腔室淨化並抽除。 在將腔室淨化和/或抽除後,在一種實施方式中, 室中執行氧電漿處理,以處理由前驅物沉積在基材上 (J 並開始下一沉積循環(例如OMCTS沉積)。在另一種 方式中,如果希望一氮摻雜氧化物或SiN層,可應用 或不加入H2的NH3電漿處理。氧電漿可由能夠産生 ' 該層表面的氧自由基的任何含氧氣體來提供。例如, . 體可包括〇2、C02、N20或它們的組合。含氧氣體可 流速注入腔室中。含氧氣體將需要一段時間注入腔室 這一時間爲大約0.1秒至約6 0秒之間,取決於介層 渠圖案剖面。氧電漿將在50W至1 000W之間的RF功 對薄 該薄 們的 例如 金屬 方法 層沉 的低 沉積 予以 將任 或抽 在腔 的層 實施 加入 氧化 該氣 以一 中, 同/溝 率以 19 200826196 13.5 6MHz的頻率提供到腔室中。可應用混 率。爲了使電漿處理對下面層(諸如低介售 衝擊或損壞減至最小’較佳地應用低的高鑛 如在大約30W至約100W之間,其對應於大 至約0.082 W/cm2之間。 通過終止流入腔室的含氧氣體可終止電 地,然後可對沉積層的厚度進行測量。隨後 (、 的流動使其流入腔室中,以沉積薄層的附加 _ 室並隨後進行上述的氧電漿處理。可以執行 電漿處理的多個循環,直至得到該層的希望 制》儿積在内連線中的層的厚度,可以控制隨 沉積的金屬線的厚度。 在另一種實施方式中,提供了一種將沉 的厚度控制在約4 A至約1 〇 〇人之間的方法。 氮表層的該基材在電漿存在的情況下暴露在 以在該基材上沉積一層,並且然後使用由含 Ο 的NH3産生的電漿,或使用由一選自由02 組成的群組中的含氧氣體産生的電聚,來處 將基材暴露在含矽前驅物下以沉積一層,以 理該層的步驟將反複進行,直到達到該層的 • 在再一實施方式中,提供了一種製造包 或氮化物的緻密介電質間隙壁的方法。該方 默存在的情況下,暴露包含閘極的已圖案化 以包含富氧或富氮表面的)至含矽前驅物, 合頻率的RF功 :常數薄膜)的 RF功率,例 約 0.033W/cm2 漿處理。可選 ,恢復前驅物 量。淨化該腔 沉積、淨化及 厚度。通過控 後在内連線中 積在基材上層 包含富氧或富 含矽前驅物, 或不含h2 、co2 和 N20 理該層。上述 及用電漿來處 帚望厚度。 含任一氧化物 法包括,在電 的基材(其可 以在該閘極上 204A-4C illustrate a trench profile of a region with a high trench density. Figure 4A shows the trench profile before ashing and before wet cleaning. 4B and 4C are diagrams showing the trench profile on which the low dielectric constant film does not have and has a thin OMCTS layer, respectively, after ashing and after wet cleaning. Figure 4B shows that for trenches in low dielectric constant films that do not have a thin OMCTS layer, wet cleaning will cause a critical dimension loss of about 30 nm. Fig. 4C shows that such a CD loss would not be observed when a low dielectric constant film of a thin OMCTS layer was deposited thereon before wet cleaning. 5A-5C illustrate a trench profile of a region with a low trench density. Figure 5A shows the trench profile before ashing and before wet cleaning. The figures $b and $c show the low dielectric constant film on which the low dielectric constant film does not have a trench profile with a 'thin 0MCTS layer' after ashing and after wet cleaning. Figure 5b: For a trench in a low dielectric constant film having no thin 0MCTS layer thereon, the wet cleaning will cause a temple &amp; ^ J paper cut of greater than about 3 〇ηη. Fig. 5C shows that such an undercut will not be observed when a thin dielectric constant film of the genus &amp; i is deposited on the thin OMCTS layer before wet cleaning. Thus, the thin OMCTS layer provides a rich main surface anti-surface which in turn provides a hydrophobic surface for preventing the loss of critical dimensions and undercutting of the low-k film during the wet etching process. We can see that the thin layer provided in accordance with an embodiment of the present invention acts as a dense sealing layer and can be used to prevent the use of such a material (such as 17 200826196 as a BARC for depositing a BARC layer later, or as a A PVP barrier precursor or an ALD precursor (e.g., ald-precursor) of the deposition barrier layer penetrates into the porous low-k film deposited thereon by the thin layer. For example, after the photoresist ashing in the via etching and the vial first damasene process, the thin layer can be deposited on the low dielectric constant film. Subsequent BARC filling can be performed on the thin layer. The thin layer provides a plugging layer for the anti-soil BARC material to penetrate into the dielectric film. Then, a dielectric barrier between the low dielectric constant film and the underlying conductor material (such as copper) will be etched to expose the underlying conductive material after trench etching and photoresist removal. After etching the dielectric barrier, a reduction chemical reaction can be used to clean the conductive surface exposed by removing the dielectric barrier and to remove oxides (such as copper oxide (C u Ο) from the surface. )). The thin layer is then deposited on the sidewalls of the vias and trenches. The thin layer provides a layer of pores that prevents subsequent barrier layer precursors from penetrating into the low dielectric constant film. In an embodiment in which a BARC layer is deposited on a thin layer after wet cleaning of the substrate, the thin layer may be post-treated with a ruthenium (or other inert gas) plasma to adjust the carbon concentration of the surface of the thin layer and the thin The wetting angle of the layer. The wetting angle can be reduced to about 7 inches. 0 or less to promote wetting and deposition of the BARC layer. Figure 6 shows that the wetting angle is reduced as the plasma treatment time increases. Use mild process conditions (eg, RF power between about 3 〇w to about 10 ' w and He flow rate between about 1 〇〇 sccm and about 1 〇〇〇〇 sccm) for plasma processing The sealing properties of the thin layer will not be destroyed. If it is necessary to adjust the surface wetting or contact angle, the post-mortem plasma treatment can also be carried out before the deposition of the other layers (e.g., the A L D barrier layer) of the BARC layer on the thin layer. Different gases can be applied to the post-pulp treatment layer, such as 〇2, C〇2, N2〇, NH3, H2, nitrogen, nitrogen, nitrogen or combinations thereof. Plasma post treatment can alter the properties and properties of the surface of the layer, surface tension and surface contact angle. In another embodiment, a method of controlling the critical dimension of an interconnect centerline is provided. As described in the previous embodiments, this involves depositing a thin layer on the patterned low dielectric constant film. The patterned dielectric constant film may comprise an oxygen-rich or nitrogen-rich surface prior to being deposited on the patterned low dielectric constant film. After this layer, the flow of the precursor (e.g., 0 M C T S ) used to deposit the layer is terminated and removed from the chamber only by injecting a carrier gas (e.g., He carrier gas) into the chamber. The chamber can be purged or the chamber cleaned and pumped out. After purging and/or pumping the chamber, in one embodiment, an oxygen plasma treatment is performed in the chamber to treat deposition of the precursor onto the substrate (J and begin the next deposition cycle (eg, OMCTS deposition). In another mode, if a nitrogen-doped oxide or SiN layer is desired, the NH3 plasma treatment of H2 may or may not be added. The oxygen plasma may be from any oxygen-containing gas capable of producing oxygen radicals on the surface of the layer. Provided. For example, the body may include 〇2, C02, N20, or a combination thereof. The oxygen-containing gas may be injected into the chamber at a flow rate. The oxygen-containing gas will take a period of time to inject into the chamber for a period of from about 0.1 second to about 60. Between seconds, depending on the profile of the via pattern, the oxygen plasma will carry out the RF work between 50W and 1 000W to the thin deposition of thin layers such as metal deposition, or to be applied to the layer of the cavity. Adding oxidized gas to the chamber, the same/ditch ratio is supplied to the chamber at a frequency of 19 200826196 13.5 6 MHz. The mixing rate can be applied. In order to make the plasma treatment to the underlying layer (such as low-merase shock or damage is minimized) Good application low As between about 30 W and about 100 W, which corresponds to between about 0.082 W/cm 2. The electrical ground can be terminated by terminating the oxygen-containing gas flowing into the chamber, and then the thickness of the deposited layer can be measured. The flow causes it to flow into the chamber to deposit a thin layer of additional chambers and subsequently perform the above-described oxygen plasma treatment. Multiple cycles of the plasma treatment can be performed until the desired layer of the layer is obtained. The thickness of the layer in the wire can control the thickness of the metal wire as it is deposited. In another embodiment, a method of controlling the thickness of the sink between about 4 A and about 1 Torr is provided. The substrate is exposed in the presence of a plasma to deposit a layer on the substrate, and then uses a plasma generated from cerium-containing NH3, or an oxygen-containing gas selected from a group consisting of 02. The resulting electropolymerization, where the substrate is exposed to a ruthenium-containing precursor to deposit a layer, the step of treating the layer will be repeated until the layer is reached. • In yet another embodiment, a manufacturing package or Density of nitride A method of electrical barriers. In the case of a silent presence, exposure of an RF containing a gated pattern containing an oxygen-rich or nitrogen-rich surface to a germanium-containing precursor, a frequency-dependent RF work: a constant film) Power, for example, about 0.033 W/cm2 slurry treatment. Optional, recovering the amount of precursors. Purifying the deposition, purification and thickness of the chamber. After controlling, the upper layer of the substrate contains an oxygen-rich or cerium-rich precursor in the upper layer. Or without h2, co2, and N20. The above and the plasma are used to look at the thickness. Any oxide method includes, on an electrical substrate (which can be on the gate 20

200826196 沉積一層,並然後用由含氧或含氮氣體(其選自由 〇2、C〇2、n2〇、含氮氣體及 nh3組成的群組,包含 包含h2 )産生的電漿來處理該層。上述含矽前驅物, 關於控制在内連線中金屬線臨界尺寸的方法的電漿處 也可用於製造緻密介電質間隙壁的方法及控制層厚度 4A至約100A之間的方法。 儘管前面對本發明的實施方式作出了描述,在不 由下面的申請專利範圍決定的本發明基本範圍的情況 可設計出其他或進一步的實施方式。 【圖式簡單說明】 因此,爲了可以詳細瞭解本發明的上述特徵,下 將參照各實施方式對主要如上概述的本發明進行更詳 述,其中一些實施方式將在附圖中進行說明。應該注 是,附圖只說明本發明的典型實施方式,因此不應將 爲對本發明範圍的限制,對本發明的其他等效實施方 是可行的。 第1A-1F圖爲示出了根據本發明的實施方式在製 序的不同階段的基材結構的截面圖; 第2圖爲示出了根據本發明的實施方式,在灰化 和之後低介電常數薄膜的介電常數(k),以及在灰化 上沉積薄OMCTS層的低介電常數薄膜的介電常數(1 曲線圖; 第3圖爲示出了根據本發明的實施方式,在灰化 包含 或不 以及 理, 在約 悖離 下, 面, 細描 意的 其視 式也 程順 之前 後其 )的 之前 21 200826196 和之後低介電常數薄膜的濕潤角,以及在灰化後其上沉積 薄OMCTS層的低介電常數薄膜的濕潤角的曲線圖; 第4A圖爲根據習知技術在灰化之後和濕式清洗之前 溝渠剖面(密集分佈)的示意圖;第4B圖爲根據習知技 術在灰化和濕式清洗之後溝渠剖面(密集分佈)的示意圖; 第4C圖爲根據本發明的一種實施方式在灰化和濕式清洗 之後溝渠剖面(密集分佈)的示意圖; 第5A圖爲根據習知技術在灰化之後和濕式清洗之前 溝渠剖面(iso結構/開口區域)的示意圖;第5B圖爲根據 習知技術在灰化和濕式清洗之後溝渠剖面(i s 〇結構/開口 區域)的示意圖;第5 C圖爲根據本發明的實施方式在灰 化和濕式清洗之後溝渠剖面(iso結構/開口區域)的示意 rgj · 圖, 第 6圖爲示出了根據本發明的實施方式的薄 OMCTS 層濕潤角相對於該層之氦電漿後處理的時間長度的作圖。 【主要元件符號說明】 100 基材 102 低介電常數薄膜 104 光阻劑 106 内連線 108 薄共形層 110 層 120 層 22200826196 deposits a layer and then treats the layer with a plasma produced from an oxygen-containing or nitrogen-containing gas (selected from the group consisting of 〇2, C〇2, n2〇, nitrogen-containing gas and nh3, containing h2) . The above-described ruthenium-containing precursor, the plasma at the method of controlling the critical dimension of the metal line in the interconnect, can also be used in a method of fabricating a dense dielectric spacer and a method of controlling the thickness of the layer from 4A to about 100A. While the foregoing is a description of the embodiments of the present invention, further or further embodiments may be devised without departing from the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS The present invention, as outlined above, will be described in more detail with reference to the various embodiments of the present invention, in which FIG. It is to be understood that the drawings are only illustrative of the exemplary embodiments of the invention, and are not intended to 1A-1F are cross-sectional views showing a substrate structure at different stages of the process according to an embodiment of the present invention; FIG. 2 is a view showing an embodiment of the present invention, after ashing and low-leveling The dielectric constant (k) of the electro-continuous film, and the dielectric constant of the low-k dielectric film on which the thin OMCTS layer is deposited on the ashing (1 graph; FIG. 3 is a view showing an embodiment according to the present invention, The ashing contains or does not matter, in the 悖 悖 , , , , , , , 视 视 视 视 视 视 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 A graph of the wetting angle of a low dielectric constant film depositing a thin OMCTS layer; FIG. 4A is a schematic view of a trench profile (dense distribution) after ashing and before wet cleaning according to the prior art; FIG. 4B is a conventional view Schematic diagram of trench profile (dense distribution) after ashing and wet cleaning; Figure 4C is a schematic diagram of trench profile (dense distribution) after ashing and wet cleaning according to an embodiment of the present invention; Schematic diagram of a trench profile (iso structure/opening region) after ashing and wet cleaning according to prior art; Figure 5B is a trench profile (is 〇 structure/opening region after ashing and wet cleaning according to conventional techniques) Schematic diagram of FIG. 5C is a schematic rgj diagram of a trench profile (iso structure/opening region) after ashing and wet cleaning according to an embodiment of the present invention, and FIG. 6 is a diagram showing an implementation according to the present invention. A plot of the thin OMCTS layer wetting angle of the mode relative to the length of the plasma post-treatment of the layer. [Main component symbol description] 100 substrate 102 low dielectric constant film 104 photoresist 106 interconnect 108 thin conformal layer 110 layer 120 layer 22

Claims (1)

200826196 十、申請專利範圍: 1. 一種在一腔室中處理一基材上之一薄膜的方法,包 含: 通過在該薄膜的一富氧或富氮表面上選擇性地沉積厚 度在4埃至1 0 0埃之間並包含矽、碳,以及選擇性地包含 氧或氮的薄層沉積來處理該薄膜,其中該層的沉積包括在 R F功率存在的條件下使包含S i、C,以及Η的一前驅物起 反應。 2. 如申請專利範圍第1項所述的方法,其中,所述前 驅物選取自由以下組成的群組:通式爲Rx-Si-(OR’)y的前 驅物,其中 R = H、CH3、CH2CH3或其他烷基,R’ = CH3、 CH2CH3或其他烧基,x的取值範圍爲0到4,y的取值範 圍爲0到4,同時x + y = 4 ;具有(Rx-Si-0-Si-Ry)z結構的有 機二矽氧烷,其中RX = CH3、CH2CH3或其他烷基,Ry = H, CH3、CH2CH3或其他烷基;包括(Rx-Si-0)y結構的環有機 矽氧烷,其中RX = CH3、CH2CH3或其他烷基;包括具有3 個或更多矽原子的環狀結構的環有機矽化合物,而且該環 狀結構可選擇性包括一個或更多氧原子;以及包括具有交 替的砍和氧原子環,及一個或兩個烧基與碎原子相結合的 環有機矽化合物。 3. 如申請專利範圍第1項所述的方法,其中,所述前 驅物包含曱基,以抑制所述薄層的繼續生長。 23 200826196 4.如申請專利範圍第1項所述的方法,其中,所述層 具有與所述薄膜的富氧或富氮表面相比更高的碳含量,同 時所述層在所述薄膜上提供了 一個碳飽和表面層。 5. 如申請專利範圍第1項所述的方法,進一步包括在 所述層沉積後濕式清洗該基材。 6. 如申請專利範圍第1項所述的方法,其中,提供的 RF功率的功率值在大約0.1 09W/cm1 2或更低。 7. 如申請專利範圍第1項所述的方法,其中,所述腔 室中的壓力爲大約1.5Torr或更高。200826196 X. Patent Application Range: 1. A method of treating a film on a substrate in a chamber comprising: selectively depositing a thickness of 4 angstroms on an oxygen-rich or nitrogen-rich surface of the film The film is treated between 10 Å and containing ruthenium, carbon, and optionally a thin layer of oxygen or nitrogen, wherein the deposition of the layer includes the inclusion of S i, C, in the presence of RF power, and A precursor of sputum reacts. 2. The method of claim 1, wherein the precursor is selected from the group consisting of: a precursor of the formula Rx-Si-(OR')y, wherein R = H, CH3 , CH2CH3 or other alkyl, R' = CH3, CH2CH3 or other alkyl groups, x ranges from 0 to 4, y ranges from 0 to 4, and x + y = 4; with (Rx-Si -0-Si-Ry)z structure of an organic dioxane wherein RX = CH3, CH2CH3 or other alkyl group, Ry = H, CH3, CH2CH3 or other alkyl group; including (Rx-Si-0)y structure a cyclic organoaluminoxane, wherein RX = CH3, CH2CH3 or other alkyl; a cyclic organotelluric compound comprising a cyclic structure having 3 or more deuterium atoms, and the cyclic structure optionally comprising one or more oxygen Atom; and a cyclic organotelluric compound comprising alternating chopped and oxygen atomic rings and one or two alkyl groups bonded to the broken atoms. 3. The method of claim 1, wherein the precursor comprises a sulfhydryl group to inhibit continued growth of the thin layer. The method of claim 1, wherein the layer has a higher carbon content than the oxygen-rich or nitrogen-rich surface of the film, while the layer is on the film A carbon saturated surface layer is provided. 5. The method of claim 1, further comprising wet cleaning the substrate after the layer is deposited. 6. The method of claim 1, wherein the power value of the supplied RF power is about 0.109 W/cm12 or less. 7. The method of claim 1, wherein the pressure in the chamber is about 1.5 Torr or higher. 8.如申請專利範圍第1項所述的方法,其中,所述腔 室中一喷頭與所述腔室中一基材支架的間隔爲大於大約 200mil 〇 9.如申請專利範圍第1項所述的方法,進一步包括應 用一種氣體來電漿後處理所述層,所述氣體選自由 〇2、 C02、N20、NH3、H2、氦、氬以及氮組成的群組。 24 1 0.如申請專利範圍第1項所述的方法,進一步包括 2 電漿後處理所述層,其中所述電漿後處理改變了所述層的 200826196 表面特性,以及,其中所述表面特性選自由表面張力以及 表面接觸角組成的群組。 11.如申請專利範圍第1項所述的方法,進一步包括 在所述層上沉積一底抗反射塗層。 1 2 ·如申請專利範圍第1項所述的方法,進一步包括 通過原子層沉積或物理氣相沉積在厚度爲4人至ιοοΑ並包 含石夕和碳,以及選擇性包括氧和/或氣的所述層上沉積一阻 障層。 13.如申請專利範圍第1項所述的方法,其中,所述 薄層提供了一個緻密層,該緻密層可防止抗反射塗層材料 以及ALD或PVD阻障層前驅物滲透到所述薄膜中。 1 4. 一種處理一基材的方法,其中該基材在其表面上沉 積有一低k介電質薄膜,該方法包括: 在RF功率存在的條件下,通過使一前驅物反應而選 擇性地在所述薄膜的一富氧或富氮表面上沉積一富碳層, 其中所述前驅物包含選自由矽、碳、氧和氮組成的群組的 元素。 1 5 .如申請專利範圍第14項所述的方法,其中,所述 富碳層的厚度在4埃至1 00埃之間。 25 200826196 1 6 ·如申請專利範圍第1 4項所述的方法,其中,所述 前驅物是自飽和的。 r 1 7.如申請專利範圍第1 4項所述的方法,其中,所述 前驅物選取自由以下組成的群組:通式爲Rx-Si-(OR’)y的 前驅物,其中R = H、CH3、CH2CH3或其他烷基,R,=CH3、 CH2CH3或其他烧基,X的取值範圍爲0到4,y的取值範 圍爲0到4,同時x + y = 4 ;具有(Rx-Si-0-Si-Ry)z結構的有 機二矽氧烷,其中RX = CH3、CH2CH3或其他烷基,Ry = H、 CH3、CH2CH3或其他烷基;包括(Rx-Si-0)y結構的環有機 矽氧烷,其中RX = CH3、CH2CH3或其他烷基;包括具有3 個或更多矽原子的環狀結構的環有機矽化合物,而且該環 狀結構可選擇性包括一個或更多氧原子;以及包括具有交 替的矽和氧原子的環,及一個或兩個烷基與矽原子相結合 的環有機矽化合物。 1 8.如申請專利範圍第1 4項所述的方法,進一步包括 應用一種氣體來電漿後處理所述富碳層,所述氣體選自由 〇2、C〇2、N2O、NH3、H2、氛、氮以及氮組成的群組。 19· 一種在一腔室中處理一基材上的一薄膜的方法, 包含: 在RF功率存在的條件下,通過使一前驅物反應而將 26 200826196 厚度在4埃至1 0 0埃之間的一富碳層沉積在所述基材的一 富氧或富氮表面上,其中,所述前驅物包含選自由矽、碳、 氧和氮組成的群組的元素。 20·如申請專利範圍第19項所述的方法,進一步包括 將所述富碳層暴露於一電漿,所述電漿係由選自由 〇2、 C02、N20、NH3、H2、氦、氬以及氮組成的群組的化合物 形成。8. The method of claim 1, wherein a spacing of a showerhead in the chamber and a substrate support in the chamber is greater than about 200 mil 〇 9. as claimed in claim 1 The method further includes post treatment of the layer with a gas selected from the group consisting of ruthenium 2, C02, N20, NH3, H2, argon, argon, and nitrogen. The method of claim 1, further comprising 2 post-treating the layer, wherein the post-treatment of the plasma changes the surface characteristics of the layer of 200826196, and wherein the surface The characteristics are selected from the group consisting of surface tension and surface contact angle. 11. The method of claim 1, further comprising depositing a bottom anti-reflective coating on the layer. 1 2 The method of claim 1, further comprising depositing by atomic layer deposition or physical vapor deposition at a thickness of 4 to ιοοΑ and including Shixia and carbon, and optionally including oxygen and/or gas. A barrier layer is deposited on the layer. The method of claim 1, wherein the thin layer provides a dense layer that prevents the anti-reflective coating material and the ALD or PVD barrier layer precursor from penetrating into the film in. 1 4. A method of treating a substrate, wherein the substrate has a low-k dielectric film deposited on a surface thereof, the method comprising: selectively reacting a precursor by reacting in the presence of RF power A carbon-rich layer is deposited on an oxygen-rich or nitrogen-rich surface of the film, wherein the precursor comprises an element selected from the group consisting of ruthenium, carbon, oxygen, and nitrogen. The method of claim 14, wherein the carbon-rich layer has a thickness of between 4 angstroms and 100 angstroms. The method of claim 14, wherein the precursor is self-saturating. The method of claim 14, wherein the precursor is selected from the group consisting of: a precursor of the formula Rx-Si-(OR')y, wherein R = H, CH3, CH2CH3 or other alkyl, R, =CH3, CH2CH3 or other alkyl groups, X ranges from 0 to 4, y ranges from 0 to 4, and x + y = 4; An organic dioxane of the Rx-Si-0-Si-Ry)z structure, wherein RX = CH3, CH2CH3 or other alkyl group, Ry = H, CH3, CH2CH3 or other alkyl group; includes (Rx-Si-0) a cyclic organic oxane of the y structure, wherein RX = CH3, CH2CH3 or other alkyl; a cyclic organofluorene compound comprising a cyclic structure having 3 or more ruthenium atoms, and the cyclic structure optionally includes one or More oxygen atoms; and a cyclic organic ruthenium compound comprising a ring having alternating ruthenium and oxygen atoms, and one or two alkyl groups bonded to a ruthenium atom. 1 8. The method of claim 14, further comprising post-treating the carbon-rich layer with a gas selected from the group consisting of 〇2, C〇2, N2O, NH3, H2, , a group of nitrogen and nitrogen. 19. A method of processing a film on a substrate in a chamber, comprising: 26, 26,196, 196, and a thickness of between 4 and 100 Å by reacting a precursor in the presence of RF power. A carbon-rich layer is deposited on an oxygen-rich or nitrogen-rich surface of the substrate, wherein the precursor comprises an element selected from the group consisting of ruthenium, carbon, oxygen, and nitrogen. 20. The method of claim 19, further comprising exposing the carbon-rich layer to a plasma selected from the group consisting of ruthenium 2, C02, N20, NH3, H2, ruthenium, argon. And a compound of the group consisting of nitrogen is formed. 2727
TW096140628A 2006-11-21 2007-10-29 Method to minimize wet etch undercuts and provide pore sealing of extreme low k (k<2.5) dielectrics TWI392024B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US86677006P 2006-11-21 2006-11-21
US11/694,856 US20070287301A1 (en) 2006-03-31 2007-03-30 Method to minimize wet etch undercuts and provide pore sealing of extreme low k (k<2.5) dielectrics

Publications (2)

Publication Number Publication Date
TW200826196A true TW200826196A (en) 2008-06-16
TWI392024B TWI392024B (en) 2013-04-01

Family

ID=39517296

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096140628A TWI392024B (en) 2006-11-21 2007-10-29 Method to minimize wet etch undercuts and provide pore sealing of extreme low k (k<2.5) dielectrics

Country Status (4)

Country Link
JP (1) JP5174435B2 (en)
KR (1) KR100939593B1 (en)
CN (1) CN100550318C (en)
TW (1) TWI392024B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101740332B (en) * 2008-11-13 2012-04-25 中芯国际集成电路制造(北京)有限公司 Etching method of semiconductor element

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8236684B2 (en) * 2008-06-27 2012-08-07 Applied Materials, Inc. Prevention and reduction of solvent and solution penetration into porous dielectrics using a thin barrier layer
US20120122320A1 (en) * 2010-11-17 2012-05-17 Applied Materials, Inc. Method Of Processing Low K Dielectric Films
US9034770B2 (en) * 2012-09-17 2015-05-19 Applied Materials, Inc. Differential silicon oxide etch
CN103839871B (en) * 2012-11-21 2017-09-08 中芯国际集成电路制造(上海)有限公司 A kind of manufacture method of semiconductor devices
CN105448705B (en) * 2014-06-18 2018-05-04 无锡华润上华科技有限公司 The method and its oxide-film of particulate on a kind of elimination chip oxide film
CN105244257B (en) * 2014-07-08 2020-06-23 中芯国际集成电路制造(上海)有限公司 Method for improving protrusion defect of porous low-k film
CN105702619A (en) * 2014-11-27 2016-06-22 中芯国际集成电路制造(上海)有限公司 Formation method of semiconductor structure
US20160225652A1 (en) 2015-02-03 2016-08-04 Applied Materials, Inc. Low temperature chuck for plasma processing systems
CN111863610A (en) * 2020-05-12 2020-10-30 中国电子科技集团公司第十一研究所 Method for preparing electrode hole and computer readable storage medium
CN113667976A (en) * 2021-08-27 2021-11-19 中国科学院兰州化学物理研究所 Corrosion-resistant DLC film with hole sealing top layer and preparation method thereof

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001077196A (en) * 1999-09-08 2001-03-23 Sony Corp Manufacture of semiconductor device
TW535253B (en) * 2000-09-08 2003-06-01 Applied Materials Inc Plasma treatment of silicon carbide films
US6890850B2 (en) * 2001-12-14 2005-05-10 Applied Materials, Inc. Method of depositing dielectric materials in damascene applications
US6936551B2 (en) * 2002-05-08 2005-08-30 Applied Materials Inc. Methods and apparatus for E-beam treatment used to fabricate integrated circuit devices
US6927178B2 (en) * 2002-07-11 2005-08-09 Applied Materials, Inc. Nitrogen-free dielectric anti-reflective coating and hardmask
US7005390B2 (en) * 2002-10-09 2006-02-28 Intel Corporation Replenishment of surface carbon and surface passivation of low-k porous silicon-based dielectric materials
KR100909175B1 (en) * 2002-12-27 2009-07-22 매그나칩 반도체 유한회사 How to form a dual damascene pattern
KR100573484B1 (en) * 2003-06-30 2006-04-24 에스티마이크로일렉트로닉스 엔.브이. Semiconductor device and a method of forming the same
KR20050014231A (en) * 2003-07-30 2005-02-07 매그나칩 반도체 유한회사 A method for forming a semiconductor device
JP2005050954A (en) * 2003-07-31 2005-02-24 Toshiba Corp Semiconductor device and manufacturing method therefor
US20050037153A1 (en) * 2003-08-14 2005-02-17 Applied Materials, Inc. Stress reduction of sioc low k films
JP4015976B2 (en) * 2003-08-28 2007-11-28 株式会社東芝 Manufacturing method of electronic device
JP2005203568A (en) * 2004-01-15 2005-07-28 Semiconductor Leading Edge Technologies Inc Fabrication process of semiconductor device, and semiconductor device
JP2006332408A (en) * 2005-05-27 2006-12-07 Sony Corp Manufacturing method of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101740332B (en) * 2008-11-13 2012-04-25 中芯国际集成电路制造(北京)有限公司 Etching method of semiconductor element

Also Published As

Publication number Publication date
CN101202227A (en) 2008-06-18
KR100939593B1 (en) 2010-02-01
KR20080046087A (en) 2008-05-26
CN100550318C (en) 2009-10-14
JP5174435B2 (en) 2013-04-03
JP2008147644A (en) 2008-06-26
TWI392024B (en) 2013-04-01

Similar Documents

Publication Publication Date Title
US8445075B2 (en) Method to minimize wet etch undercuts and provide pore sealing of extreme low k (k&lt;2.5) dielectrics
TWI392024B (en) Method to minimize wet etch undercuts and provide pore sealing of extreme low k (k&lt;2.5) dielectrics
KR102524573B1 (en) Formation of SiOCN thin films
US11107673B2 (en) Formation of SiOCN thin films
KR102376352B1 (en) Method and composition for providing pore sealing layer on porous low dielectric constant films
CN1522313A (en) Method for improving nucleation and adhesion of cvd and ald films deposited onto low-dielectric-constant dielectrics
US20210287936A1 (en) Method for filling recessed features in semiconductor devices with a low-resistivity metal
JP2011526078A (en) Prevention and reduction of solvent and solution penetration into porous dielectrics using thin barrier layers
TW201300567A (en) Dielectric recovery of plasma damaged low-k films by UV-assisted photochemical deposition
JP6821607B2 (en) Wiring integration for side wall pore sealing and via cleanliness
TW202403076A (en) Selective deposition of organic material