JP5164273B2 - マルチダイ集積回路デバイス - Google Patents
マルチダイ集積回路デバイス Download PDFInfo
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- JP5164273B2 JP5164273B2 JP2009153602A JP2009153602A JP5164273B2 JP 5164273 B2 JP5164273 B2 JP 5164273B2 JP 2009153602 A JP2009153602 A JP 2009153602A JP 2009153602 A JP2009153602 A JP 2009153602A JP 5164273 B2 JP5164273 B2 JP 5164273B2
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- H—ELECTRICITY
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5286—Arrangements of power or ground buses
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Description
Claims (15)
- 第2ダイに連結された第1ダイと、
前記第2ダイを貫通するよう設けられ、前記第1ダイに電力リファレンスを供給する複数のビアと
を備え、
前記貫通する複数のビアは、前記第2ダイの複数の回路セクションに重なることなく第1軸の方向の複数の線に沿って設けられ、前記複数の線は、前記第2ダイの前記複数の回路セクションを有する2つ以上のトラックの間且つ前記2つ以上のトラックに平行であり、
前記貫通する複数のビアは、前記2つ以上のトラックの両側に設けられ、
前記第2ダイは、少なくとも第1メタル層、第2メタル層および第3メタル層を含み、
前記第1メタル層、前記第2メタル層、前記第3メタル層の順に、前記第2ダイの回路に近く、
前記第1メタル層を利用して前記複数のビアの複数のコンタクトパッドが提供され、
前記第2メタル層を利用して同様のビア同士を連結して、
前記第3メタル層を利用して複数の回路セクションの部分同士をインターコネクトし、
前記第1ダイは、互いに間隔があいた複数のメタル層を含み、
前記第1ダイおよび前記第2ダイは、互いに隣接するよう設けられ、
前記第1ダイの前記複数のメタル層は、前記第2ダイの複数のメタル層と隣接する、
装置。 - 前記第2ダイの複数の回路セクションは、前記第1軸に平行である、請求項1に記載の装置。
- 前記第2ダイは、メモリチップである、請求項1または2に記載の装置。
- 前記複数のビアのそれぞれは、前記第1軸に平行な関連線に沿って設けられる、請求項1から3の何れか一項に記載の装置。
- 前記複数の回路セクションは、1以上のメモリバンクに構成された、互いに間隔があいた複数のメモリセクションである、請求項1から4の何れか一項に記載の装置。
- 前記第3メタル層の配線は、間隙を有し、
前記間隙は、前記第2メタル層からの接続を受け、貫通させる、請求項1から5の何れか一項に記載の装置。 - 前記第1メタル層内の配線および前記第3メタル層内の配線は、同じ方向に配列され、前記第2メタル層の配線と直交するよう配列される、請求項1から6の何れか一項に記載の装置。
- 複数の回路コンポーネントを有する基板と、
前記基板を通る複数の貫通シリコンビアのランドパッドを有するメタル層と
を備え、
前記複数の貫通シリコンビアのランドパッドは、前記複数の回路コンポーネントを有する複数のトラックに平行な複数の線に沿って設けられ、
前記複数の貫通シリコンビアのランドパッドは、前記複数のトラックに重なることなく前記複数のトラックの間且つ前記複数のトラックの両側に設けられ、
少なくとも第1メタル層、第2メタル層および第3メタル層を有し、前記第1メタル層、前記第2メタル層、前記第3メタル層の順に、チップの前記複数の回路コンポーネントに近く、
前記第1メタル層を利用して前記複数の貫通シリコンビアの複数のコンタクトパッドが提供され、
前記第2メタル層を利用して同様の貫通シリコンビア同士を連結して、
前記第3メタル層を利用して複数の回路コンポーネントの部分同士をインターコネクトし、
前記チップは、互いに間隔があいた複数のメタル層を含み、
前記チップおよび別のダイは、互いに隣接するよう設けられ、
前記チップの前記複数のメタル層は、前記別のダイの複数のメタル層と隣接する、
チップ。 - 前記複数の回路コンポーネントは、複数のメモリバンクに構成されている、請求項8に記載のチップ。
- 前記複数の貫通シリコンビアのランドパッドの少なくとも幾つかは、第2チップの複数のメタル配線に連結される、請求項8または9に記載のチップ。
- 前記複数の回路コンポーネントは、1つのバンク内の互いに間隔があいた複数のメモリバンクセクションに構成されている、請求項8から10の何れか一項に記載のチップ。
- ICパッケージであって、
各々が互いに間隔があいた複数のメモリバンクセクションを含む複数のメモリバンクを含むメモリダイに、積層構成で連結されたプロセッサダイと、
前記メモリダイを貫通するよう設けられ、前記プロセッサおよび複数のメモリダイに、前記ICパッケージの外から電力リファレンスを供給する複数の貫通シリコンビアと
を備え、
前記複数のメモリバンクセクションは複数のトラック内に配置され、
前記複数の貫通シリコンビアは、前記複数のトラックに重なることなく前記複数のトラックの間且つ前記複数のトラックの両側に設けられ、
前記メモリダイは、少なくとも第1メタル層、第2メタル層、および第3メタル層を含み、
前記第1メタル層、前記第2メタル層、前記第3メタル層の順に、前記メモリダイの回路に近く、
前記第1メタル層を利用して前記複数の貫通シリコンビアの複数のランドパッドが提供され、
前記第2メタル層を利用して同様の貫通シリコンビア同士を連結して、
前記第3メタル層を利用して前記複数のメモリバンクセクションの部分同士をインターコネクトし、
前記プロセッサダイは、互いに間隔があいた複数のメタル層を含み、
前記プロセッサダイおよび前記メモリダイは、互いに隣接するよう設けられ、
前記プロセッサダイの前記複数のメタル層は、前記メモリダイの複数のメタル層と隣接する、
ICパッケージ。 - 前記複数のメモリバンクセクションの軸は、前記複数の貫通シリコンビアのトラックに平行である、請求項12に記載のICパッケージ。
- 前記第3メタル層の配線は、間隙を有し、
前記間隙は、前記第2メタル層からの接続を受け、前記プロセッサダイの1以上のメタル配線へと貫通させる、請求項12または13に記載のICパッケージ。 - 前記第1メタル層内の配線および前記第3メタル層内の配線は、同じ方向に配列され、前記第2メタル層の前記配線と直交するよう配列される、請求項12から14の何れか一項に記載のICパッケージ。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/215,761 | 2008-06-30 | ||
US12/215,761 US8283771B2 (en) | 2008-06-30 | 2008-06-30 | Multi-die integrated circuit device and method |
Publications (2)
Publication Number | Publication Date |
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JP2010016377A JP2010016377A (ja) | 2010-01-21 |
JP5164273B2 true JP5164273B2 (ja) | 2013-03-21 |
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Application Number | Title | Priority Date | Filing Date |
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JP2009153602A Expired - Fee Related JP5164273B2 (ja) | 2008-06-30 | 2009-06-29 | マルチダイ集積回路デバイス |
Country Status (5)
Country | Link |
---|---|
US (1) | US8283771B2 (ja) |
JP (1) | JP5164273B2 (ja) |
KR (1) | KR101073709B1 (ja) |
CN (1) | CN101621055B (ja) |
DE (1) | DE102009030524B4 (ja) |
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JP4287294B2 (ja) | 2004-01-21 | 2009-07-01 | 株式会社東芝 | 自動設計方法、自動設計装置、及び半導体集積回路 |
US7453150B1 (en) * | 2004-04-01 | 2008-11-18 | Rensselaer Polytechnic Institute | Three-dimensional face-to-face integration assembly |
JP4421957B2 (ja) * | 2004-06-29 | 2010-02-24 | 日本電気株式会社 | 3次元半導体装置 |
JP4561235B2 (ja) | 2004-08-20 | 2010-10-13 | 富士通株式会社 | 半導体装置の設計方法 |
JP2007036104A (ja) * | 2005-07-29 | 2007-02-08 | Nec Electronics Corp | 半導体装置およびその製造方法 |
JP4859513B2 (ja) | 2006-04-19 | 2012-01-25 | 新光電気工業株式会社 | 配線設計方法及びその設計装置 |
KR100871381B1 (ko) * | 2007-06-20 | 2008-12-02 | 주식회사 하이닉스반도체 | 관통 실리콘 비아 칩 스택 패키지 |
US7466028B1 (en) * | 2007-10-16 | 2008-12-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor contact structure |
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2008
- 2008-06-30 US US12/215,761 patent/US8283771B2/en active Active
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- 2009-06-29 JP JP2009153602A patent/JP5164273B2/ja not_active Expired - Fee Related
- 2009-06-30 KR KR1020090058782A patent/KR101073709B1/ko active IP Right Grant
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DE102009030524A1 (de) | 2010-01-21 |
US20090321893A1 (en) | 2009-12-31 |
US8283771B2 (en) | 2012-10-09 |
KR20100003237A (ko) | 2010-01-07 |
DE102009030524B4 (de) | 2022-10-27 |
CN101621055B (zh) | 2012-07-04 |
CN101621055A (zh) | 2010-01-06 |
JP2010016377A (ja) | 2010-01-21 |
KR101073709B1 (ko) | 2011-10-14 |
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