CN101621055A - 多管芯集成电路器件和方法 - Google Patents

多管芯集成电路器件和方法 Download PDF

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CN101621055A
CN101621055A CN200910139648A CN200910139648A CN101621055A CN 101621055 A CN101621055 A CN 101621055A CN 200910139648 A CN200910139648 A CN 200910139648A CN 200910139648 A CN200910139648 A CN 200910139648A CN 101621055 A CN101621055 A CN 101621055A
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tube core
memory
tsv
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CN101621055B (zh
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D·索马谢卡尔
T·卡尔尼克
J·徐
Y·叶
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Intel Corp
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Abstract

在一些实施例中，提供了一种具有耦合到第二管芯的第一管芯的集成电路。第二管芯具有穿过其设置的穿硅通孔，以向第一管芯提供参考电源。穿硅通孔能够横向重新定位，而不妨碍第二管芯中的电路区段。

Description

多管芯集成电路器件和方法
背景技术
如图1所示，可以将两个(或多个)管芯叠置在通常称为三维集成电路封装的结构中，以提供第一管芯(例如处理器)105和第二管芯(例如存储器)107之间的密集互连(例如3000个或更多互连)，这提供了管芯之间的提高的带宽。不过，为了向管芯(尤其是上方的第一管芯)提供信号和电源线，可以采用向上穿过第二(下方)管芯的穿硅通孔(TSV)109。
在一些实施例中，第一(上方)管芯为处理器，而第二(下方)管芯包括密集存储器件。下方管芯上的凸点连接到封装衬底，封装衬底将封装耦合到诸如母板的外部连接。图2A为存储器管芯107的示范性高阶布局图。将存储器布置成个体的存储体(存储体205)。存储器管芯还包括外围I/O电路块以及中间的逻辑、时钟和定时电路块。从存储器管芯的背侧处理穿硅通孔，并且所述穿硅通孔着落在例如与上方(处理器)管芯之间的界面处预先分配的接触焊盘上。
图2B示出了一种为着落于整个存储器管芯上的TSV定位接触焊盘的可能方式。令人遗憾的是，如图所示，TSV穿过存储体区段并结束于各种不对称或不规则的位置。因此，希望有改进的方案。
附图说明
在附图中以举例方式而非限制方式例示了本发明的实施例，在附图中类似的附图标记表示类似的元件。
图1是具有两个管芯的常规三维集成电路(IC)封装的透视截面图。
图2A是用于图1的IC的存储器管芯中的存储体的布局图。
图2B示出了图2A的布局图，示出了将信号耦合到IC封装中的两个管芯的穿硅通孔(TSV)的位置。
图3是根据一些实施例的具有TSV的存储器管芯的布局图。
图4A是根据另一些实施例的具有TSV的存储器管芯的布局图。
图4B是根据一些实施例的具有如图4A所示的第一管芯和第二存储器管芯的IC封装的侧视图。
具体实施方式
图3示出了具有存储器区段205和TSV的存储器管芯(芯片)的一些实施例的布局。存储器区段(阵列)设置于TSV周围。相对于之前讨论的实施例，如图所示，减小了存储体的尺寸，并将TSV(或通孔)设置于空白空间内。这种方式的一个优点是节省了逻辑、时钟和定时电路(也分布在空间中但该图中未示出)的空间。
不过，在一些情况下，即使正在设计封装配置的时候，电路(例如存储器)的设计也可能演变，因此希望TSV设置的规格同时改变。例如，在3D叠置体中，一个管芯上的TSV规格可能由规格也可能变化的其他管芯支配。这意味着存储体，尤其是存储单元阵列，可能需要在其区域之内容纳TSV。令人遗憾的是，存储器一般被设计成密集的。因此，不能轻易连累到存储器的布置，例如在要移动TSV的位置时，这可能是侵入性(intrusive)的，有时是对存储器阵列设计的干扰。
图4A和4B示出了用于在多管芯IC叠置体中实现TSV的另一种方式。图4A是根据一些实施例的具有TSV的存储器管芯的布局图，图4B示出了IC封装的侧视图。(注意，对于本公开内容中的所有附图而言，存储体和TSV不是按比例绘制的。实际的TSV着落区域通常小于图示。)如图所示，将存储体405(该图中示出了十二个存储体)分成间隔开的区段417。对于如图所示设置的存储体而言，区段之间的空间排列形成轨迹419(为了简洁起见未示出所有轨迹)以包含TSV。在图示的实施例中，轨迹419彼此间隔且平行排列(沿着X轴)。(注意，如本文所使用的，术语“轨迹”用于描述例如纵向形状的空间，例如细长的矩形。该术语未必指代任何物理结构。)
利用这种设置，可以在轨迹中的任何地方容纳TSV。亦即，它们可以象征性地在轨迹之内“滑动”，使得设计人员有横向移动通孔的更大灵活性，即使在稍后的IC封装开发阶段期间也是如此。(从设计的角度来看，TSV是“可滑动的”，但一旦制造之后它们实际上不移动。)这意味着也可以在任何位置沿其“轨迹”移动存储体区段417，而不会显著影响到三维工艺开发或TSV定位规格的变化。
图4B示出了通过众多，例如超过3000个互连触点而在管芯互连409处耦合在一起的第一和第二管芯402、406。第一和第二管芯具有衬底(分别为403，407)，在衬底上形成它们的电路，且从衬底开始，它们均具有图示实施例中的金属化层M1到M7，用于对管芯之内和之间的电路元件进行互连并从TSV分配信号和参考电源。管芯402、406耦合在一起，使得它们的金属层彼此相邻，以实现更高效的互连。
典型地，每个金属层包括间隔开的沿相同方向延伸的金属线。通常，给定层中的线相对于相邻层中的线是正交的，使得彼此相邻的层中的金属线通常彼此交叉。(并非一直是这种情况；不过，如下文所述，例如，第二管芯407中的M1和M2层都在Y方向上。)在图4B中，利用虚线和实线反映出这一点。亦即，虚线代表具有沿Y轴排列的线的层，而实线代表具有沿X轴排列的线的金属层。
在图示的实施例中，M1层充当接触层，辅助TSV着落到焊盘上。M2线用于将给定线中的期望的TSV触点彼此耦合到一起。例如，可以将线中的VSS触点彼此耦合，可以将线中的VCC触点彼此耦合。TSV焊盘周围的空白区域可用于转发器、逻辑、定时、时钟缓冲器等。然后可以将M3线用于将存储体中的分离区段耦合到一起，且在一些实施例中，在M3线之内保留空间(或间隙)，以允许TSV连接从M2线上行，例如，耦合到第一管芯402。
在之前的描述中，已经阐述了很多具体细节。然而，要理解可以不用这些具体细节来实践本发明的实施例。在其他情况下，可能没有具体示出公知的电路、结构和技术，以免混淆对说明书的理解。有鉴于此，提到“一个实施例”、“实施例”、“范例实施例”、“各实施例”等表示这样描述的本发明实施例可以包括特定特征、结构或特性，但并非每个实施例都必然包括特定特征、结构或特性。此外，一些实施例可以具有针对其他实施例描述的一些特征、全部特征或没有任何这样的特征。
在前面的描述和后面的权利要求中，以下术语应当进行如下理解：可以使用术语“耦合”和“连接”及其派生词。应当理解，这些术语并非意在用作彼此的同义词。相反，在特定实施例中，使用“连接”表示两个或更多元件彼此直接物理或电接触。使用“耦合”表示两个或更多元件彼此协作或交互，但它们可以直接物理或电接触或不接触。
本发明不限于所述实施例，而是可以利用所附权利要求的精神和范围之内的修改和变化加以实践。例如，应当认识到，本发明适于与所有类型的半导体集成电路(“IC”)芯片一起使用。这些IC芯片的范例包括，但不限于处理器、控制器、芯片组部件、可编程逻辑阵列(PLA)、存储器芯片、网络芯片等。
还应当认识到，在一些附图中，用线条表示信号导体线。一些线条可以更粗，以表示较多的成分信号路径，一些线条具有若干标记，以表示若干成分信号路径，和/或在一个或多个末端具有箭头，以表示基本信息流方向。不过，不应将这视为限制的方式。相反，可以结合一个或多个示范性实施例使用这种增添的细节来帮助更容易地理解电路。无论是否具有额外信息，任何图示的信号线实际上都可以包括可以沿多个方向行进的一个或多个信号，并可以利用任何适当类型的信号方案实现信号线，信号方案例如是用差分对、光纤线和/或单端线实现的数字或模拟线。
应当认识到，可能已经给出了范例尺寸/型号/值/范围，但本发明不限于此。随着制造技术(例如光刻)的日趋成熟，人们期望能够制造更小尺寸的装置。此外，为了图示和论述简单，在附图中可以示出或不示出公知的IC芯片和其他部件的电源/接地连接，以免使本发明难于理解。此外，为了避免使本发明难于理解，并且鉴于如下事实：关于方框图设置的实施的细节高度依赖于要实施本发明的平台，即，这种细节应当处于本领域技术人员的知识范围之内，可以以方框图的形式示出这种设置。在为了描述本发明的范例实施例而给出具体细节(例如电路)的情况下，本领域的技术人员应当明白，可以改变或不改变这些具体细节来实践本发明。因此应将说明书视为例示性的而不是限制性的。

Claims (19)

1、一种设备，包括：
第一管芯，所述第一管芯耦合到第二管芯；
穿过所述第二管芯设置的通孔，用于向所述第一管芯提供参考电源，能够沿第一轴横向重新定位所述通孔而不妨碍所述第二管芯中的电路区段。
2、根据权利要求1所述的设备，其中所述第二管芯电路区段能够沿所述第一轴重新定位。
3、根据权利要求1所述的设备，其中所述第二管芯为存储器芯片。
4、根据权利要求1所述的设备，其中所述通孔均沿着平行于所述第一轴的相关线排列。
5、根据权利要求1所述的设备，其中所述电路区段是布置成一个或多个存储体的间隔开的存储器区段。
6、根据权利要求1所述的设备，其中所述第二管芯至少具有第一、第二和第三金属线层，第一金属线层较靠近所述第二管芯中的电路，接着是第二和第三金属线层，其中所述第一层用于为所述通孔提供接触焊盘，所述第二层用于将类似的通孔耦合到一起，所述第三层用于将电路区段的部分彼此互连。
7、根据权利要求6所述的设备，其中所述第三金属层中的线具有间隙，以允许来自所述第二金属层的连接从中穿过。
8、根据权利要求6所述的设备，其中所述第一和第三层中的线沿相同方向排列并与所述第二金属线层中的线正交排列。
9、根据权利要求6所述的设备，其中所述第一管芯具有间隔开的金属线层，所述第一和第二管芯彼此相邻安装，使得所述第一管芯的金属线层与所述第二管芯的金属线层相邻。
10、一种芯片，包括：
具有电路部件的衬底；以及
金属层，所述金属层具有多个用于穿过所述衬底的穿硅通孔(TSV)的TSV着落焊盘，所述着落焊盘沿着平行于用于包含所述电路部件的轨迹的线设置，其中所述TSV能够沿着它们的线重新定位而不影响电路元件。
11、根据权利要求10所述的芯片，其中将所述电路部件布置成存储体。
12、根据权利要求11所述的芯片，其中至少一些接触焊盘耦合到第二芯片中的金属线。
13、根据权利要求11所述的芯片，其中将所述电路部件布置成给定存储体之内彼此间隔开的存储体区段。
14、一种集成电路(IC)封装，包括：
叠置配置的耦合到存储器管芯的处理器管芯，所述存储器管芯具有存储体，每个存储体包括间隔开的存储体区段；
穿过所述存储器管芯设置的穿硅通孔(TSV)，用于从所述集成电路封装外部向所述处理器和存储器管芯提供参考电源，所述TSV能够平行于轨迹重新定位而不妨碍所述存储体区段。
15、根据权利要求14所述的IC封装，其中所述存储体区段能够沿着平行于所述TSV轨迹的轨迹重新定位。
16、根据权利要求15所述的IC封装，其中所述存储器管芯至少具有第一、第二和第三金属线层，所述第一金属线层较靠近所述存储器管芯中的电路，接着是所述第二和第三金属线层，其中所述第一层用于为所述TSV提供着落焊盘，所述第二层用于将类似的TSV耦合到一起，所述第三层用于将所述存储体区段的部分彼此互连。
17、根据权利要求16所述的IC封装，其中所述第三金属层中的线具有间隙，以允许来自所述第二金属层的连接从中穿过，从而到达所述处理器管芯中的一个或多个金属线。
18、根据权利要求16所述的IC封装，其中所述第一和第三层中的线沿相同方向排列并与所述第二金属线层中的线正交排列。
19、根据权利要求16所述的IC芯片，其中所述处理器管芯具有间隔开的金属线层，所述第一和第二管芯彼此相邻安装，使得所述处理器管芯的金属线层与所述存储器管芯的金属线层相邻。
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