CN109643706A - 嵌入式管芯的互连 - Google Patents

嵌入式管芯的互连 Download PDF

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Publication number
CN109643706A
CN109643706A CN201780051816.9A CN201780051816A CN109643706A CN 109643706 A CN109643706 A CN 109643706A CN 201780051816 A CN201780051816 A CN 201780051816A CN 109643706 A CN109643706 A CN 109643706A
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CN
China
Prior art keywords
sub
core
tube core
main pipe
tube
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201780051816.9A
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English (en)
Inventor
L·Y·富
C·K·支
M·S·陈
W·L·李
W·L·吴
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Altera Corp
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Altera Corp
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Application filed by Altera Corp filed Critical Altera Corp
Publication of CN109643706A publication Critical patent/CN109643706A/zh
Pending legal-status Critical Current

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Abstract

提供了与集成电路器件有关的器件和方法。集成电路器件包括母管芯和子管芯，其中嵌入的子管芯位于集成电路器件的衬底中。母管芯和子管芯的微凸块接合在一起以形成母管芯和子管芯之间的直接向下连接。

Description

嵌入式管芯的互连
背景技术
本公开一般涉及具有一个或多个嵌入式管芯的集成电路器件。更具体地，本公开涉及直接连接到另一个管芯的嵌入式管芯。
该部分旨在向读者介绍可能与下面描述和/或要求保护的本公开的各个方面有关的技术的各个方面。相信该讨论有助于向读者提供背景信息以促进更好地理解本公开的各个方面。因此，应该理解，这些陈述应该从这个角度来阅读，而不是作为现有技术的承认。
集成电路(IC)采用各种形式。这些IC通常使用管芯形成。管芯是电路位于其上的一小块半导体材料(例如硅)。管芯上的电路可以执行特定功能(例如，运算放大器)或更多通用功能，例如处理器或可编程设备(例如，现场可编程门阵列(FPGA))。一个或多个管芯可以一起封装在集成电路(IC)中。封装的IC为一个或多个管芯及其电路提供保护。封装还可以从封装外部提供与一个或多个管芯的可接入连接和/或提供管芯之间的互连。然而，这些到管芯和/或管芯之间的连接可以控制由集成电路执行的功能的延迟。具体而言，较长的连接和连接的较低密度会增加这些连接的延迟。提供这种互连的一种方法包括使用硅通孔(TSV)。然而，TSV的制造成本高，其中，在集成电路器件的制造期间具有相对高水平的技术问题和实现的复杂性。
发明内容
本文公开的某些实施方案的概述如下。应当理解，呈现这些方面仅仅是为了向读者提供这些特定实施例的简要概述，并且这些方面不旨在限制本公开的范围。实际上，本公开可以包含可能未在下面阐述的各种方面。
本发明的实施例涉及用于在集成电路(IC)器件封装中直接连接母管芯和子管芯的系统、方法和设备。如下所述，一个或多个子管芯嵌入IC器件封装的衬底中，在母管芯和一个或多个子管芯的每个相应管芯之间提供短而高密度的互连路径，而不使用硅通孔(TSV)。具体地，母管芯和子管芯可以与它们彼此面对的微凸块对齐。这些微凸块从母管芯和子管芯延伸以彼此接合，以形成具有高密度互连的直接通孔向下互连。母管芯和子管芯可以通过IC器件封装中的电路或也通过衬底中的微孔连接。
以上提到的特征的各种改进可以与本公开的各个方面相关地存在。其他特征也可以包含在这些不同方面中。这些改进和附加特征可以单独存在或以任何组合存在。例如，以下关于所示实施例中的一个或多个讨论的各种特征可以单独或以任何组合结合到本发明的任何上述方面中。以上呈现的简要概述仅旨在使读者熟悉本公开的实施例的某些方面和上下文，而不限于所要求保护的主题。
附图说明
通过阅读以下详细描述并参考附图，可以更好地理解本公开的各个方面，其中：
图1是根据实施例的其中具有多个管芯的集成电路器件的框图；
图2是根据实施例的在相邻管芯之间具有半导体互连的集成电路器件封装的框图；
图3是根据实施例的具有堆叠管芯的面对面布置的集成电路器件封装的框图；
图4是根据实施例的具有嵌入式子管芯的集成电路器件封装的框图；
图5是示出了根据实施例的图4的集成电路器件封装的布局的框图；
图6是示出了根据实施例的图4的集成电路器件封装的布局的框图；以及
图7是根据实施例的用于形成图4的集成电路器件封装的过程的流程图。
具体实施方式
下面将描述一个或多个具体实施例。为了提供这些实施例的简明描述，并未在说明书中描述实际实现的所有特征。应当意识到，在任何此类实际实现的开发中，如在项目/产品的任何工程或设计中，必须做出许多特定于实现的决策以实现开发者的特定目标，例如遵从系统相关和业务相关的约束，这可能因实现而不同。此外，应当意识到，这种开发努力可能是复杂且耗时的，但是对于受益于本公开的普通技术人员来说仍然是设计、加工和制造的常规任务。
如下面进一步详细讨论的，本公开的实施例总体上涉及在集成电路(IC)器件封装中直接连接母管芯和嵌入子管芯。母管芯可以是主要驱动IC器件封装的功能的管芯。附加地或替代地，母管芯通常可以是物理上大于IC器件封装中的其他管芯的管芯。如下所述，一个或多个子管芯嵌入IC器件封装的衬底中，在母管芯和一个或多个子管芯之间提供短的互连路径，而不使用硅通孔(TSV)。具体地，母管芯和子管芯可以与它们彼此面对的微凸块对齐。从母管芯和子管芯延伸的这些微凸块可以彼此接合以形成具有高密度互连的直接通孔向下互连。
由于母管芯和相应的子管芯对准使得微凸块彼此接合，因此母管芯和相应的子管芯重叠一定距离。这种重叠减小了IC器件封装的总体占用面积，而没有降低功能并且显著增加了驱动母管芯和相应管芯的复杂性。
由于一个或多个子管芯嵌入在衬底中，因此可以使用衬底上的表面布线或者在衬底的一个或多个层中布线而不是仅通过母管芯来访问一个或多个子管芯。该连接方案降低了母管芯的复杂性，因为可以不依赖母管芯来提供对一个或多个子管芯的所有功率和所有通信。
此外，在制造的整个过程中，由于一个或多个子管芯嵌入在衬底中，因此在一些实施例中可以仅使用一个芯片附接工艺。具体地，在芯片附接工艺中，只有母管芯可以连接到衬底。此外，由于只有母管芯未被进行底部填充，因此降低了母管芯底部填充的复杂性。
图1示出了集成电路(IC)器件10的实施例，其包括在IC器件10中封装在一起的母管芯12和一个或多个子管芯14。母管芯12可以是设置在半导体衬底上的任何电路。例如，母管芯12可以包括处理电路，例如在中央处理单元(CPU)或可编程电路中找到的处理电路。在另一示例中，母管芯12可包括可编程逻辑器件的可编程逻辑电路，例如现场可编程门阵列(FPGA)。附加地或替代地，母管芯12可以包括与一个或多个子管芯14中的其他电路相互作用的任何电路。类似地，子管芯14可以包括与母管芯12的电路互连的任何电路(例如，CPU、FPGA、存储器、收发器等)。然后将IC器件10封装在一起以保护电路免受外部元件的影响或分配由管芯12和14的电路生成的热量。该封装还便于连接到母管芯12和一个或多个子管芯14。
图2示出了集成电路(IC)器件封装50，其包括连接母管芯54和子管芯56的嵌入式互连桥52。嵌入式互连桥52嵌入在IC器件封装50的衬底58中。管芯54和56通过互连桥52通过微凸块60彼此耦合。互连桥52能够以比使用TSV更低的制造成本或者复杂性实现母管芯54和子管芯56之间的高密度连接。然而，通过互连桥52的路径相对较长，从而使母管芯54和子管芯56之间的接合定时闭合变得复杂。此外，IC器件封装50的占用面积可能相对较大。具体地，通过母管芯54和子管芯56彼此相邻定位以及由互连桥52贡献的尺寸增加，IC器件封装50的占用面积更大。
IC器件封装50的形成包括将母管芯54和子管芯56分别耦合到衬底58中的嵌入式互连桥52。母管54或子管芯56的每个单独耦合包括各个管芯可能无法正确附接的潜在风险。
IC器件封装50包括将相应的管芯54和56耦合到衬底58的管芯凸块62。然后使用底部填充物64对管芯54和56进行底部填充。底部填充物64可以是电绝缘粘合剂。底部填充物64增加了衬底58与管芯54和56之间的连接的机械强度。底部填充物64减少了管芯54和56与衬底58之间的热膨胀不匹配。底部填充物64可以在连接的边缘处分配。然后使用毛细管作用在器件下面流动以使底部填充物64在管芯凸块62之间流动。在IC器件封装50中，底部填充物64在母管芯54和子管芯56下面流动。每个底部填充物在制造IC器件封装50中引入了困难。此外，并联或串联地对管芯54和56进行底部填充可能比对单个管芯进行底部填充更复杂。
IC器件封装50包括焊球66，焊球66布置在二维平面中以提供IC器件封装50到外部器件的互连位置。每个焊球66提供可以进行外部连接的位置，以便输入到IC器件封装50中的电路或从IC器件封装50中的电路输出。
图3示出了集成电路(IC)器件封装70，其包括在IC器件封装70的衬底76上方以面对面取向定向的母管芯72和子管芯74。母管芯72和子管芯74的面通过微凸块78通过直接连接来进行连接。母管芯72和子管芯74的面对面堆叠使母管芯72和子管芯74之间的直接和短接合距离成为可能。但是，所有到子管芯74的连接经由管芯凸块80通过母管芯72达成。IC器件封装70包括底部填充物82，其与图1的底部填充物64类似地工作。IC器件封装70还包括类似于图2的焊球66的焊球84。
尽管IC器件封装70使用母管芯72和子管芯74之间的短互连路径。然而，组装过程相对复杂且昂贵。例如，IC器件封装70的热压缩增加了制造工艺可能出错的另一个故障点并增加了组装成本。而且，类似于IC器件封装50，IC器件封装70包括母管芯72和子管芯74的单独附件。IC器件封装70还包括比在前面讨论过的IC器件封装50的底部填充工艺期间可能发生的更多潜在困难和故障。
图4示出了集成电路(IC)器件封装90，其包括耦合到两个嵌入式子管芯94和96的母管芯92。尽管仅示出了两个嵌入式子管芯94，但IC器件封装90可包括任何数量的能够与母管芯92物理连接的嵌入式子管芯94、96。每个子管芯94、96面向母管芯92定向。
此外，母管芯92与子管芯94、96对准，使得母管芯92的微凸块98和一个或多个子管芯94、96彼此接合以形成从母管芯92到子管芯94、96的直接向下通孔。直接向下连接是相对短的通路，其在母管芯92和子管芯94、96之间提供高密度互连。这种直接向下连接允许高带宽通信而不会增加母管芯和子管芯94、96之间的定时接口的关闭的复杂性。此外，直接向下连接的短小可以包括比较长的互连路径改善的信号完整性。
母管芯92还具有管芯凸块100，管芯凸块100将母管芯92耦合到衬底102，通过衬底102可以形成与外部电路的连接。子管芯94、96可以经由布线104连接到外部电路。布线104可以包括衬底102中用于表面布线的层，表面布线允许直接键合(例如，连接)到IC器件封装90之外。例如，布线104可以将子管芯94、96耦合到焊球106，焊球106提供接口，通过该接口可以直接连接到子管芯94、96。换句话说，使用布线104，IC器件封装90便于直接连接到子管芯94、96，而无需通过母管芯92连接。这种直接连接可以特别有用于提供电源和接地连接而不通过母管芯92提供这种电源，因为通过母管芯92的这种连接可能利用额外的再分配层和/或增加母管芯92的功耗。此外，IC器件封装90还可以通过衬底102提供通过焊球106到母管芯92的连接。虽然前面讨论过使用球栅阵列中的焊球106，但是在一些实施例中，IC器件封装90可以包括其他封装类型，例如通孔封装、表面安装封装、管芯载体封装、针栅阵列封装、栅格阵列封装、扁平封装和/或其他合适的封装类型。
IC器件封装90还包括底部填充物108，其功能类似于图2和图3的底部填充物64和82。然而，由于底部填充物108仅位于母管芯92下方，所以底部填充物108仅在单个管芯下流动。由于底部填充物108仅在单个管芯下流动而不是在多于一个管芯下流动，因此底部填充物108的表面积可以更小并且底部填充物108可以更快地执行而具有更少的不适当应用的机会(例如，不适当的流动)和/或质量或可靠性问题。
此外，如图所示，母管芯92是经历芯片附接工艺的唯一管芯，其中母管92附接到衬底102。由于仅芯片附接单个管芯，因此该工艺比利用多个管芯附接工艺简单。此外，由于仅附接母管芯92，因此管芯附接工艺失败的机会较少。
此外，IC器件封装90利用三维封装，在母管芯92和相应的子管芯94、96之间具有至少一些重叠。这种重叠减小了IC器件封装90在封装上的实现的总体占位面积尺寸，使用相同的管芯封装彼此相邻。尺寸是电子器件的重要因素。为了尝试通过扩展摩尔定律以适应单个管芯内的更多晶体管来实现更高的系统性能，可以使用三维封装来在单个器件内高度集成系统。然而，由于重叠仅包括子管芯94、96的一部分，因此可以直接访问子管芯94、96而不会使与母管芯92的连接复杂化。
尽管IC器件封装90仅示出了两个子管芯94、96，但是由于母管芯92的边缘上可用的空间可以允许，因此许多子管芯可以与母管芯92接合。例如，图5示出了布局109，其包括母管芯110、子管芯111、112、113和114在母管芯110的每一侧上耦合到母管芯110。具体地，子管芯111、112、113和114分别在重叠区域115、116、117和118中耦合到母管芯110。相应子管芯的母管芯110的微凸块可以在母管芯110和相应子管芯之间的相应重叠区域中与相应子管芯的微凸块接合。例如，子管芯111可以使用在重叠区域115中接合的母管芯11 0和子管芯111的微凸块耦合到母管芯110。在另一示例中，母管芯110可以使用衬底102中的微孔连接到子管芯111。
此外，附接的子管芯可以在尺寸和/或功能上与其他子管芯不同。例如，图6示出了具有母管芯122的布局120。母管芯122可以包括CPU，可编程器件[例如，现场可编程门阵列(FPGA))或一些其他电路。母管芯122耦合到大的子管芯124。大的子管芯124可以包括可以与母管芯122接合的可编程器件(例如，FPGA)。母管芯122也可以与具有各种其他形状和尺寸的其他子管芯126、128、130、132和134耦合，每个形状和尺寸与母管芯122重叠并与母管芯122接合。子管芯126、128、130、132和134可包括任何合适的电路，例如放大器、多路复用、传感、逻辑门、定时器、稳压器、电机控制器、微控制器、微处理器、FPGA和其他电路。
图7示出了用于制造集成电路(IC)器件的过程200。过程200包括将一个或多个子管芯嵌入集成电路器件的衬底中(框202)。如前所述，一个或多个子管芯和/或母管芯92可以包括任何合适的电路，例如放大器、多路复用、传感、逻辑门、定时器、电压调节器、电机控制器、微控制器、微处理器、FPGA，以及其他电路。此外，一个或多个子管芯可以位于衬底中，使得一个或多个子管芯是共面的。子管芯的共面方面可包括一个或多个子管芯的主体或一个或多个子管芯的微凸块或两者。例如，如果所有一个或多个子管芯的微凸块长度相等，则一个或多个子管芯的顶表面(更靠近母管芯92)可以是共面的，而每个微凸块的每个尖端可以是也是共面的。但是，如果一个或多个子管芯的微凸块的长度不相等，则微凸块的尖端或一个或多个子管芯的顶面可以是共面的。附加地或替代地，一个或多个子管芯中的至少一个可以位于由剩余的一个或多个子管芯限定的平面之外。例如，可以进行这样的布置以适应母管芯92的微凸块长度的差异或其他考虑因素，以确保母管芯92的微凸块与一个或多个子管芯的相应微凸块之间的连通。
将母管芯92与一个或多个子管芯对准包括将母管芯92的一部分与一个或多个子管芯中的每一个重叠。一个或多个子管芯各自具有部分位于母管芯92下方的重叠部分和从母管芯下方延伸出的剩余延伸部分。一个或多个子管芯中的每一个的该延伸部分提供到相应的一个或多个子管芯的接入点。使用该接入点，可以在衬底中形成布线，以提供对一个或多个子管芯中的每一个的延伸部分的接入，并且因此提供对相应的一个或多个子管芯的内部电路的接入。
通过将母管芯92的微凸块与一个或多个子管芯的相应微凸块接合，工艺200继续将母管芯92垂直地对准在一个或多个子管芯上方(框204)。该对准使用母管芯92的微凸块和一个或多个子管芯中的每一个的微凸块提供母管芯92与一个或多个子管芯中的每一个之间的接合。母管芯92和子管芯可以与母管芯和一个或多个子管芯之间的微孔连接。母管芯92和每个子管芯之间的界面提供包括高密度连接的直接向下连接(例如，没有硅通孔)。
一旦母管芯92与一个或多个子管芯对准，母管芯92就附着到衬底上(框206)。例如，母管芯92可以使用底部填充和/或焊料附接到衬底。此外，附接可以包括到衬底或通过衬底的电连接。结合机构(例如，焊球)为母管芯92中和/或一个或多个子管芯的各种管芯中的各种电路提供接入点。例如，焊球可以布置在球栅阵列中，每个球提供到位于母管芯内或一个或多个子管芯中的一个的电路的连接点。作为球栅阵列的补充或替代，集成电路器件可以包括其他类型的封装，例如通孔封装、表面安装封装、芯片载体封装、针栅阵列封装、平面栅格阵列封装、扁平封装，以及/或其他合适的封装类型。
虽然本公开中阐述的实施例可以容许各种修改和替代形式，但是在附图中通过示例的方式示出了特定实施例，并且已经在本文中对其进行了详细描述。然而，应该理解的是，本公开不旨在限于所公开的特定形式。本公开内容将覆盖落入由以下所附权利要求限定的本公开的精神和范围内的所有修改、等同物和替代物。

Claims (20)

1.一种集成电路器件封装，包括：
衬底；
耦合到所述衬底的第一管芯，其具有：
内部电路；以及
多个第一管芯微凸块，其提供从第一管芯外部的与所述内部电路的电连接；以及
嵌入在所述衬底中的第二管芯并且其具有：
多个第二管芯微凸块，其中，第一组第一管芯微凸块与第一组第二管芯微凸块接合，以在所述第一管芯和所述第二管芯之间提供直接向下连接。
2.根据权利要求1所述的集成电路器件封装，其中，所述第一管芯包括中央处理单元，并且所述第二管芯包括可编程逻辑器件。
3.根据权利要求2所述的集成电路器件封装，其中，所述可编程逻辑器件包括现场可编程门阵列。
4.根据权利要求1所述的集成电路器件封装，其中，所述第一管芯包括可编程逻辑器件。
5.如权利要求4所述的集成电路器件封装，其中，所述可编程逻辑器件包括现场可编程门阵列。
6.根据权利要求1至5中任一项所述的集成电路器件封装，其中，所述第一管芯在垂直方向上与所述第二管芯重叠。
7.根据权利要求6所述的集成电路器件封装，其中，所述第一管芯在水平方向上延伸超出所述第二管芯的边缘。
8.根据权利要求1所述的集成电路器件，其中，所述第一管芯使用管芯凸块耦合到所述衬底。
9.根据权利要求1或8所述的集成电路器件，包括布线，所述布线提供通过所述衬底的对所述第二管芯的接入。
10.一种集成电路器件，包括：
嵌入在衬底中的一个或多个子管芯；
母管芯，其在所述一个或多个子管芯的垂直上方，并且在相应的一个或多个重叠区域中仅重叠所述一个或多个子管芯中的每一个的一部分；以及
所述母管芯和所述一个或多个子管芯之间的一个或多个互连路径，每个互连路径发生在相应的一个或多个重叠区域中。
11.根据权利要求10所述的集成电路器件，包括布线，所述布线提供从所述集成电路装置外部的通过所述衬底的对所述一个或多个子管芯中的至少一个的接入。
12.根据权利要求10或11所述的集成电路器件，其中，所述一个或多个子管芯中的每一个的所述部分各自包含所述一个或多个子管芯的微凸块区域，所述微凸块区域各自包含一个或多个微凸块，所述微凸块各自提供从所述母管芯到所述一个或多个子管芯中的相应一个的连通。
13.根据权利要求12所述的集成电路器件，其中，所述微凸块区域包括所述一个或多个子管芯中的相应一个的边缘。
14.一种用于封装集成电路器件的方法，包括：
将子管芯嵌入衬底中；
将母管芯垂直地在所述子管芯上方对准，其中，所述子管芯的微凸块与所述母管芯的微凸块接合，以在所述子管芯和所述母管芯之间建立连接；以及
将所述母管芯附接到所述衬底。
15.根据权利要求14所述的方法，其中，嵌入所述子管芯包括将一个或多个另外的子管芯嵌入所述衬底中，并且其中，将所述母管芯与所述子管芯对准包括将所述母管芯与所述一个或多个另外的子管芯对准。
16.根据权利要求15所述的方法，其中，所述一个或多个另外的子管芯与所述子管芯共面嵌入。
17.根据权利要求14或15所述的方法，其中，使所述母管芯与所述子管芯对准包括将所述母管芯与所述子管芯的重叠部分重叠，其中，所述子管芯的剩余部分从所述母管芯下方延伸。
18.根据权利要求17所述的方法，包括在所述衬底中形成布线以提供对所述子管芯的剩余部分的接入。
19.根据权利要求14或15所述的方法，包括使用所述母管芯的管芯凸块将所述母管芯耦合到所述衬底。
20.根据权利要求14或15所述的方法，包括使用所述衬底中的微孔将所述母管芯耦合到所述子管芯。
CN201780051816.9A 2016-09-28 2017-09-15 嵌入式管芯的互连 Pending CN109643706A (zh)

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