JP5147779B2 - 配線基板の製造方法及び半導体パッケージの製造方法 - Google Patents

配線基板の製造方法及び半導体パッケージの製造方法 Download PDF

Info

Publication number
JP5147779B2
JP5147779B2 JP2009099989A JP2009099989A JP5147779B2 JP 5147779 B2 JP5147779 B2 JP 5147779B2 JP 2009099989 A JP2009099989 A JP 2009099989A JP 2009099989 A JP2009099989 A JP 2009099989A JP 5147779 B2 JP5147779 B2 JP 5147779B2
Authority
JP
Japan
Prior art keywords
layer
metal layer
wiring board
wiring
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2009099989A
Other languages
English (en)
Japanese (ja)
Other versions
JP2010251552A5 (enExample
JP2010251552A (ja
Inventor
幸太郎 小谷
順一 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2009099989A priority Critical patent/JP5147779B2/ja
Priority to US12/755,555 priority patent/US8458900B2/en
Priority to TW99111229A priority patent/TWI472283B/zh
Priority to KR1020100034673A priority patent/KR101709629B1/ko
Publication of JP2010251552A publication Critical patent/JP2010251552A/ja
Publication of JP2010251552A5 publication Critical patent/JP2010251552A5/ja
Application granted granted Critical
Publication of JP5147779B2 publication Critical patent/JP5147779B2/ja
Priority to US13/892,416 priority patent/US9018538B2/en
Priority to US14/673,981 priority patent/US20150206833A1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113—Via provided in pad; Pad over filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0367—Metallic bump or raised conductor not used as solder bump
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10242—Metallic cylinders
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0376—Etching temporary metallic carrier substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2009099989A 2009-04-16 2009-04-16 配線基板の製造方法及び半導体パッケージの製造方法 Active JP5147779B2 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2009099989A JP5147779B2 (ja) 2009-04-16 2009-04-16 配線基板の製造方法及び半導体パッケージの製造方法
US12/755,555 US8458900B2 (en) 2009-04-16 2010-04-07 Wiring substrate having columnar protruding part
TW99111229A TWI472283B (zh) 2009-04-16 2010-04-12 具有柱狀突出部分之配線基板
KR1020100034673A KR101709629B1 (ko) 2009-04-16 2010-04-15 기둥 형상의 돌출부를 가지는 배선 기판 제조 방법
US13/892,416 US9018538B2 (en) 2009-04-16 2013-05-13 Wiring substrate having columnar protruding part
US14/673,981 US20150206833A1 (en) 2009-04-16 2015-03-31 Wiring substrate having columnar protruding part

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009099989A JP5147779B2 (ja) 2009-04-16 2009-04-16 配線基板の製造方法及び半導体パッケージの製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2012222420A Division JP5422718B2 (ja) 2012-10-04 2012-10-04 配線基板及び半導体パッケージ

Publications (3)

Publication Number Publication Date
JP2010251552A JP2010251552A (ja) 2010-11-04
JP2010251552A5 JP2010251552A5 (enExample) 2012-05-10
JP5147779B2 true JP5147779B2 (ja) 2013-02-20

Family

ID=42980152

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009099989A Active JP5147779B2 (ja) 2009-04-16 2009-04-16 配線基板の製造方法及び半導体パッケージの製造方法

Country Status (4)

Country Link
US (3) US8458900B2 (enExample)
JP (1) JP5147779B2 (enExample)
KR (1) KR101709629B1 (enExample)
TW (1) TWI472283B (enExample)

Families Citing this family (60)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5147779B2 (ja) * 2009-04-16 2013-02-20 新光電気工業株式会社 配線基板の製造方法及び半導体パッケージの製造方法
US8698303B2 (en) 2010-11-23 2014-04-15 Ibiden Co., Ltd. Substrate for mounting semiconductor, semiconductor device and method for manufacturing semiconductor device
TWI454320B (zh) * 2011-08-19 2014-10-01 Jieng Tai Internat Electric Corp 填補穿孔的方法
JP5861400B2 (ja) * 2011-11-09 2016-02-16 イビデン株式会社 半導体実装部材
KR101287742B1 (ko) * 2011-11-23 2013-07-18 삼성전기주식회사 인쇄 회로 기판 및 그 제조 방법
JP5886617B2 (ja) * 2011-12-02 2016-03-16 新光電気工業株式会社 配線基板及びその製造方法、半導体パッケージ
JP2013247201A (ja) * 2012-05-24 2013-12-09 Shinko Electric Ind Co Ltd 配線基板、実装構造、及び配線基板の製造方法
TWI637467B (zh) * 2012-05-24 2018-10-01 欣興電子股份有限公司 中介基材及其製作方法
US9269681B2 (en) * 2012-11-16 2016-02-23 Qualcomm Incorporated Surface finish on trace for a thermal compression flip chip (TCFC)
US9299649B2 (en) 2013-02-08 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US8802504B1 (en) * 2013-03-14 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
CN104219867A (zh) * 2013-05-31 2014-12-17 宏启胜精密电子(秦皇岛)有限公司 电路板及其制作方法
US8981842B1 (en) * 2013-10-25 2015-03-17 Taiwan Semiconductor Manufacturing Company Limited Integrated circuit comprising buffer chain
KR20150064976A (ko) * 2013-12-04 2015-06-12 삼성전기주식회사 인쇄회로기판 및 그 제조방법
US20150195912A1 (en) 2014-01-08 2015-07-09 Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. Substrates With Ultra Fine Pitch Flip Chip Bumps
JP6543887B2 (ja) * 2014-02-24 2019-07-17 日立化成株式会社 バンプ付き配線基板及びその製造方法
US9693455B1 (en) * 2014-03-27 2017-06-27 STATS ChipPAC Pte. Ltd. Integrated circuit packaging system with plated copper posts and method of manufacture thereof
US20150279815A1 (en) * 2014-03-28 2015-10-01 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Substrate Having Conductive Columns
JP2016021496A (ja) * 2014-07-15 2016-02-04 イビデン株式会社 配線基板及びその製造方法
WO2016021516A1 (ja) * 2014-08-04 2016-02-11 国立研究開発法人産業技術総合研究所 局在型表面プラズモン共鳴センシングチップおよび局在型表面プラズモン共鳴センシングシステム
JP5795415B1 (ja) 2014-08-29 2015-10-14 新光電気工業株式会社 配線基板及びその製造方法
TWI562275B (en) * 2014-11-27 2016-12-11 Advance Process Integrate Technology Ltd Process of forming waferless interposer
US9899248B2 (en) * 2014-12-03 2018-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor packages having through package vias
US10325853B2 (en) * 2014-12-03 2019-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor packages having through package vias
TWI595810B (zh) * 2015-05-22 2017-08-11 欣興電子股份有限公司 封裝結構及其製作方法
CN106298707B (zh) * 2015-06-05 2019-05-21 欣兴电子股份有限公司 封装结构及其制作方法
US9755030B2 (en) * 2015-12-17 2017-09-05 International Business Machines Corporation Method for reduced source and drain contact to gate stack capacitance
WO2017187747A1 (ja) * 2016-04-28 2017-11-02 株式会社村田製作所 弾性波装置
CN107424973B (zh) * 2016-05-23 2020-01-21 凤凰先驱股份有限公司 封装基板及其制法
JP2018032661A (ja) * 2016-08-22 2018-03-01 イビデン株式会社 プリント配線板およびその製造方法
CN107872929B (zh) * 2016-09-27 2021-02-05 欣兴电子股份有限公司 线路板与其制作方法
US9922924B1 (en) * 2016-11-03 2018-03-20 Micron Technology, Inc. Interposer and semiconductor package
US9922845B1 (en) * 2016-11-03 2018-03-20 Micron Technology, Inc. Semiconductor package and fabrication method thereof
KR101944997B1 (ko) * 2017-01-06 2019-02-01 조인셋 주식회사 금속패드 인터페이스
TWI644598B (zh) * 2017-04-21 2018-12-11 南亞電路板股份有限公司 電路板結構及其形成方法
TWI643532B (zh) * 2017-05-04 2018-12-01 南亞電路板股份有限公司 電路板結構及其製造方法
US10325842B2 (en) * 2017-09-08 2019-06-18 Advanced Semiconductor Engineering, Inc. Substrate for packaging a semiconductor device package and a method of manufacturing the same
US10515889B2 (en) 2017-10-13 2019-12-24 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same
US10163758B1 (en) * 2017-10-30 2018-12-25 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method for the same
JP2019140174A (ja) * 2018-02-07 2019-08-22 イビデン株式会社 プリント配線板およびプリント配線板の製造方法
US10573572B2 (en) 2018-07-19 2020-02-25 Advanced Semiconductor Engineering, Inc. Electronic device and method for manufacturing a semiconductor package structure
KR102530754B1 (ko) * 2018-08-24 2023-05-10 삼성전자주식회사 재배선층을 갖는 반도체 패키지 제조 방법
JP7154913B2 (ja) * 2018-09-25 2022-10-18 株式会社東芝 半導体装置及びその製造方法
US11109481B2 (en) * 2019-02-15 2021-08-31 Ibiden Co., Ltd. Method for manufacturing printed wiring board and printed wiring board
WO2020203724A1 (ja) * 2019-03-29 2020-10-08 株式会社村田製作所 樹脂多層基板、および樹脂多層基板の製造方法
JP2020188209A (ja) * 2019-05-16 2020-11-19 イビデン株式会社 プリント配線板とプリント配線板の製造方法
WO2021031125A1 (zh) * 2019-08-20 2021-02-25 华为技术有限公司 线路嵌入式基板、芯片封装结构及基板制备方法
CN112885806B (zh) * 2019-11-29 2022-03-08 长鑫存储技术有限公司 基板及其制备方法、芯片封装结构及其封装方法
JP2021093417A (ja) * 2019-12-09 2021-06-17 イビデン株式会社 プリント配線板、及び、プリント配線板の製造方法
JP7512594B2 (ja) * 2020-01-10 2024-07-09 Ｔｏｐｐａｎホールディングス株式会社 回路基板
JP2021132068A (ja) * 2020-02-18 2021-09-09 イビデン株式会社 プリント配線板、プリント配線板の製造方法
KR102852871B1 (ko) * 2020-07-15 2025-09-02 삼성전자주식회사 반도체 패키지 장치
US12191161B2 (en) 2020-12-23 2025-01-07 Intel Corporation Multi-step isotropic etch patterning of thick copper layers for forming high aspect-ratio conductors
US20220312591A1 (en) * 2021-03-26 2022-09-29 Juniper Networks, Inc. Substrate with conductive pads and conductive layers
US12119319B2 (en) * 2021-12-13 2024-10-15 Amkor Technology Singapore Holding Pte. Ltd. Electronic devices and methods of manufacturing electronic devices
CN116528466A (zh) * 2022-01-21 2023-08-01 奥特斯奥地利科技与系统技术有限公司 具有突出部的部件承载件和制造方法
TWI831123B (zh) * 2022-01-28 2024-02-01 巨擘科技股份有限公司 多層基板表面處理層結構
JP2024031745A (ja) * 2022-08-23 2024-03-07 サムソン エレクトロ－メカニックス カンパニーリミテッド． プリント回路基板
CN117794104A (zh) * 2022-09-21 2024-03-29 鹏鼎控股(深圳)股份有限公司 电路板及其制造方法
CN118431159B (zh) * 2024-07-05 2024-09-10 纳宇半导体材料(宁波)有限责任公司 一种增强微凸点可靠性的封装结构及其制备方法

Family Cites Families (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3726002A (en) * 1971-08-27 1973-04-10 Ibm Process for forming a multi-layer glass-metal module adaptable for integral mounting to a dissimilar refractory substrate
US4240198A (en) * 1979-02-21 1980-12-23 International Telephone And Telegraph Corporation Method of making conductive elastomer connector
US5054192A (en) * 1987-05-21 1991-10-08 Cray Computer Corporation Lead bonding of chips to circuit boards and circuit boards to circuit boards
US4847136A (en) * 1988-03-21 1989-07-11 Hughes Aircraft Company Thermal expansion mismatch forgivable printed wiring board for ceramic leadless chip carrier
US5399898A (en) * 1992-07-17 1995-03-21 Lsi Logic Corporation Multi-chip semiconductor arrangements using flip chip dies
US5229647A (en) * 1991-03-27 1993-07-20 Micron Technology, Inc. High density data storage using stacked wafers
US5334804A (en) * 1992-11-17 1994-08-02 Fujitsu Limited Wire interconnect structures for connecting an integrated circuit to a substrate
JPH08236654A (ja) * 1995-02-23 1996-09-13 Matsushita Electric Ind Co Ltd チップキャリアとその製造方法
US6809421B1 (en) * 1996-12-02 2004-10-26 Kabushiki Kaisha Toshiba Multichip semiconductor device, chip therefor and method of formation thereof
US5900674A (en) * 1996-12-23 1999-05-04 General Electric Company Interface structures for electronic devices
US6002168A (en) * 1997-11-25 1999-12-14 Tessera, Inc. Microelectronic component with rigid interposer
US6057600A (en) * 1997-11-27 2000-05-02 Kyocera Corporation Structure for mounting a high-frequency package
US6054772A (en) * 1998-04-29 2000-04-25 National Semiconductor Corporation Chip sized package
JP3825181B2 (ja) * 1998-08-20 2006-09-20 沖電気工業株式会社 半導体装置の製造方法及び半導体装置
US6329713B1 (en) * 1998-10-21 2001-12-11 International Business Machines Corporation Integrated circuit chip carrier assembly comprising a stiffener attached to a dielectric substrate
IL128200A (en) * 1999-01-24 2003-11-23 Amitec Advanced Multilayer Int Chip carrier substrate
JP3973340B2 (ja) 1999-10-05 2007-09-12 Ｎｅｃエレクトロニクス株式会社 半導体装置、配線基板、及び、それらの製造方法
JP2001144204A (ja) * 1999-11-16 2001-05-25 Nec Corp 半導体装置及びその製造方法
JP3629178B2 (ja) * 2000-02-21 2005-03-16 Ｎｅｃエレクトロニクス株式会社 フリップチップ型半導体装置及びその製造方法
US6441479B1 (en) * 2000-03-02 2002-08-27 Micron Technology, Inc. System-on-a-chip with multi-layered metallized through-hole interconnection
JP3677429B2 (ja) * 2000-03-09 2005-08-03 Ｎｅｃエレクトロニクス株式会社 フリップチップ型半導体装置の製造方法
DE10031204A1 (de) * 2000-06-27 2002-01-17 Infineon Technologies Ag Systemträger für Halbleiterchips und elektronische Bauteile sowie Herstellungsverfahren für einen Systemträger und für elektronische Bauteile
JP3653452B2 (ja) 2000-07-31 2005-05-25 株式会社ノース 配線回路基板とその製造方法と半導体集積回路装置とその製造方法
JP2002111185A (ja) * 2000-10-03 2002-04-12 Sony Chem Corp バンプ付き配線回路基板及びその製造方法
JP3546961B2 (ja) 2000-10-18 2004-07-28 日本電気株式会社 半導体装置搭載用配線基板およびその製造方法、並びに半導体パッケージ
US6673653B2 (en) * 2001-02-23 2004-01-06 Eaglestone Partners I, Llc Wafer-interposer using a ceramic substrate
JP3875867B2 (ja) * 2001-10-15 2007-01-31 新光電気工業株式会社 シリコン基板の穴形成方法
JP3874669B2 (ja) 2002-01-25 2007-01-31 日本特殊陶業株式会社 配線基板の製造方法
US6908784B1 (en) * 2002-03-06 2005-06-21 Micron Technology, Inc. Method for fabricating encapsulated semiconductor components
JP4268434B2 (ja) * 2003-04-09 2009-05-27 大日本印刷株式会社 配線基板の製造方法
JP4708148B2 (ja) * 2005-10-07 2011-06-22 ルネサスエレクトロニクス株式会社 半導体装置
JP2007165513A (ja) * 2005-12-13 2007-06-28 Shinko Electric Ind Co Ltd 半導体装置用の多層配線基板の製造方法及び半導体装置の製造方法
KR100782798B1 (ko) * 2006-02-22 2007-12-05 삼성전기주식회사 기판 패키지 및 그 제조 방법
JP2008091639A (ja) * 2006-10-02 2008-04-17 Nec Electronics Corp 電子装置およびその製造方法
KR100832651B1 (ko) * 2007-06-20 2008-05-27 삼성전기주식회사 인쇄회로기판
US20090056998A1 (en) * 2007-08-31 2009-03-05 International Business Machines Corporation Methods for manufacturing a semi-buried via and articles comprising the same
KR100992181B1 (ko) * 2007-12-26 2010-11-04 삼성전기주식회사 패키지용 기판 및 그 제조방법
JP4835629B2 (ja) * 2008-04-11 2011-12-14 凸版印刷株式会社 半導体装置の製造方法
KR20100065691A (ko) 2008-12-08 2010-06-17 삼성전기주식회사 금속범프를 갖는 인쇄회로기판 및 그 제조방법
JP5147779B2 (ja) * 2009-04-16 2013-02-20 新光電気工業株式会社 配線基板の製造方法及び半導体パッケージの製造方法

Also Published As

Publication number Publication date
KR101709629B1 (ko) 2017-02-23
US8458900B2 (en) 2013-06-11
US20150206833A1 (en) 2015-07-23
US20100263923A1 (en) 2010-10-21
TWI472283B (zh) 2015-02-01
KR20100114845A (ko) 2010-10-26
US9018538B2 (en) 2015-04-28
US20130250533A1 (en) 2013-09-26
TW201041472A (en) 2010-11-16
JP2010251552A (ja) 2010-11-04

Similar Documents

Publication Publication Date Title
JP5147779B2 (ja) 配線基板の製造方法及び半導体パッケージの製造方法
JP5026400B2 (ja) 配線基板及びその製造方法
JP6076653B2 (ja) 電子部品内蔵基板及び電子部品内蔵基板の製造方法
JP5221315B2 (ja) 配線基板及びその製造方法
JP5421254B2 (ja) ピン・インタフェースを有する多層配線エレメント
US7435680B2 (en) Method of manufacturing a circuit substrate and method of manufacturing an electronic parts packaging structure
JP4619223B2 (ja) 半導体パッケージ及びその製造方法
US8749073B2 (en) Wiring board, method of manufacturing the same, and semiconductor device
JP5951414B2 (ja) 電子部品内蔵基板及び電子部品内蔵基板の製造方法
US20100139962A1 (en) Wiring board and method of manufacturing the same
CN101683006B (zh) 电子部件内置线路板及其制造方法
JP2005217225A (ja) 半導体装置及びその製造方法
JP2017163027A (ja) 配線基板、半導体装置及び配線基板の製造方法
KR101011339B1 (ko) 배선기판 제조방법
JP2011014944A (ja) 電子部品実装構造体の製造方法
JP4769056B2 (ja) 配線基板及びその製法方法
JP5422718B2 (ja) 配線基板及び半導体パッケージ
JP5653144B2 (ja) 半導体パッケージの製造方法
JP2023005616A (ja) 配線基板
JP3975887B2 (ja) フィルムキャリア及びその製造方法
JP2018032802A (ja) 配線基板およびこれを用いた半導体素子の実装構造

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120314

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20120314

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20120726

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120807

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20121004

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20121113

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20121127

R150 Certificate of patent or registration of utility model

Ref document number: 5147779

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20151207

Year of fee payment: 3