JP5134779B2 - 遅延同期回路 - Google Patents

遅延同期回路 Download PDF

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Publication number
JP5134779B2
JP5134779B2 JP2006067243A JP2006067243A JP5134779B2 JP 5134779 B2 JP5134779 B2 JP 5134779B2 JP 2006067243 A JP2006067243 A JP 2006067243A JP 2006067243 A JP2006067243 A JP 2006067243A JP 5134779 B2 JP5134779 B2 JP 5134779B2
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JP
Japan
Prior art keywords
signal
circuit
locked loop
delay
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2006067243A
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English (en)
Japanese (ja)
Other versions
JP2007243877A (ja
JP2007243877A5 (enExample
Inventor
高司 川本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2006067243A priority Critical patent/JP5134779B2/ja
Priority to TW095145171A priority patent/TWI399038B/zh
Priority to CN2006101566680A priority patent/CN101039108B/zh
Priority to US11/648,652 priority patent/US7482850B2/en
Priority to KR1020070002478A priority patent/KR20070093322A/ko
Priority to EP07000456.9A priority patent/EP1835623B1/en
Publication of JP2007243877A publication Critical patent/JP2007243877A/ja
Priority to US12/354,391 priority patent/US7675334B2/en
Publication of JP2007243877A5 publication Critical patent/JP2007243877A5/ja
Application granted granted Critical
Publication of JP5134779B2 publication Critical patent/JP5134779B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/085Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • AHUMAN NECESSITIES
    • A23FOODS OR FOODSTUFFS; TREATMENT THEREOF, NOT COVERED BY OTHER CLASSES
    • A23NMACHINES OR APPARATUS FOR TREATING HARVESTED FRUIT, VEGETABLES OR FLOWER BULBS IN BULK, NOT OTHERWISE PROVIDED FOR; PEELING VEGETABLES OR FRUIT IN BULK; APPARATUS FOR PREPARING ANIMAL FEEDING- STUFFS
    • A23N5/00Machines for hulling, husking or cracking nuts
    • A23N5/08Machines for hulling, husking or cracking nuts for removing fleshy or fibrous hulls of nuts
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B02CRUSHING, PULVERISING, OR DISINTEGRATING; PREPARATORY TREATMENT OF GRAIN FOR MILLING
    • B02CCRUSHING, PULVERISING, OR DISINTEGRATING IN GENERAL; MILLING GRAIN
    • B02C4/00Crushing or disintegrating by roller mills
    • B02C4/28Details
    • B02C4/30Shape or construction of rollers
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B02CRUSHING, PULVERISING, OR DISINTEGRATING; PREPARATORY TREATMENT OF GRAIN FOR MILLING
    • B02CCRUSHING, PULVERISING, OR DISINTEGRATING IN GENERAL; MILLING GRAIN
    • B02C4/00Crushing or disintegrating by roller mills
    • B02C4/28Details
    • B02C4/42Driving mechanisms; Roller speed control
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/081Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/10Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range

Landscapes

  • Engineering & Computer Science (AREA)
  • Food Science & Technology (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • Polymers & Plastics (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Pulse Circuits (AREA)
  • Dram (AREA)
JP2006067243A 2006-03-13 2006-03-13 遅延同期回路 Expired - Fee Related JP5134779B2 (ja)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP2006067243A JP5134779B2 (ja) 2006-03-13 2006-03-13 遅延同期回路
TW095145171A TWI399038B (zh) 2006-03-13 2006-12-05 Delay synchronous circuit and semiconductor integrated circuit device
CN2006101566680A CN101039108B (zh) 2006-03-13 2006-12-30 延迟同步电路及半导体集成电路器件
US11/648,652 US7482850B2 (en) 2006-03-13 2007-01-03 Delay locked loop circuit and semiconductor integrated circuit device
KR1020070002478A KR20070093322A (ko) 2006-03-13 2007-01-09 지연동기회로 및 반도체 집적회로장치
EP07000456.9A EP1835623B1 (en) 2006-03-13 2007-01-10 Delay locked loop circuit and semiconductor integrated circuit device
US12/354,391 US7675334B2 (en) 2006-03-13 2009-01-15 Delay locked loop circuit and semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006067243A JP5134779B2 (ja) 2006-03-13 2006-03-13 遅延同期回路

Publications (3)

Publication Number Publication Date
JP2007243877A JP2007243877A (ja) 2007-09-20
JP2007243877A5 JP2007243877A5 (enExample) 2009-03-12
JP5134779B2 true JP5134779B2 (ja) 2013-01-30

Family

ID=38050939

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006067243A Expired - Fee Related JP5134779B2 (ja) 2006-03-13 2006-03-13 遅延同期回路

Country Status (6)

Country Link
US (2) US7482850B2 (enExample)
EP (1) EP1835623B1 (enExample)
JP (1) JP5134779B2 (enExample)
KR (1) KR20070093322A (enExample)
CN (1) CN101039108B (enExample)
TW (1) TWI399038B (enExample)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8169241B2 (en) 2008-01-15 2012-05-01 Atmel Rousset S.A.S. Proportional phase comparator and method for phase-aligning digital signals
JP2009278528A (ja) * 2008-05-16 2009-11-26 Elpida Memory Inc Dll回路、および半導体装置
KR100996175B1 (ko) * 2008-12-26 2010-11-24 주식회사 하이닉스반도체 반도체 장치
KR101012678B1 (ko) * 2009-02-04 2011-02-09 연세대학교 산학협력단 지연 동기 루프 및 이를 포함하는 전자 장치
TWI474184B (zh) * 2009-06-08 2015-02-21 Via Tech Inc 通用序列匯流排裝置與系統
JP5588254B2 (ja) 2009-08-04 2014-09-10 キヤノン株式会社 遅延同期ループ回路
TWI396386B (zh) * 2010-05-06 2013-05-11 Princeton Technology Corp 可整合於晶片中之單擊電路、可縮短啟動時間之發射器及其方法
US8248124B2 (en) * 2010-06-03 2012-08-21 Intel Corporation Methods and apparatuses for delay-locked loops and phase-locked loops
KR102053352B1 (ko) * 2013-02-25 2019-12-09 삼성전자주식회사 고조파 락을 방지할 수 있는 위상 동기 루프 및 이를 포함하는 장치들
KR101657339B1 (ko) * 2013-05-22 2016-09-19 매그나칩 반도체 유한회사 Dll 동작 모드 제어회로 및 그 방법
US9584105B1 (en) * 2016-03-10 2017-02-28 Analog Devices, Inc. Timing generator for generating high resolution pulses having arbitrary widths
JP6390683B2 (ja) * 2016-09-28 2018-09-19 ミツミ電機株式会社 半導体集積回路
WO2018208990A1 (en) * 2017-05-09 2018-11-15 The Regents Of The University Of California Systems and methods for low-power near-field-communication
WO2019036519A1 (en) 2017-08-14 2019-02-21 The Regents Of The University Of California LOAD-INDUCED RESONANCE DISPLACEMENT MODULATION SCHEME FOR SIMULTANEOUS TRANSMISSION OF NEAR-FIELD WIRELESS ENERGY AND DATA THROUGH A PAIR OF INDUCTIVE COIL
US11527992B2 (en) 2019-09-19 2022-12-13 Analog Devices International Unlimited Company Rotary traveling wave oscillators with distributed stubs
CN113179099B (zh) * 2020-09-18 2022-04-01 上海司南卫星导航技术股份有限公司 一种锁相环电路和其控制方法、半导体器件及电子设备
US11539353B2 (en) * 2021-02-02 2022-12-27 Analog Devices International Unlimited Company RTWO-based frequency multiplier
US11323124B1 (en) 2021-06-01 2022-05-03 SambaNova Systems, Inc. Variable-length clock stretcher with correction for glitches due to finite DLL bandwidth
CN113381753B (zh) * 2021-06-08 2022-07-12 天津大学 用于延迟锁相环的启动电路

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6098727A (ja) * 1983-11-04 1985-06-01 Mitsubishi Electric Corp 同期はずれ検出回路
JPS62247624A (ja) * 1986-04-07 1987-10-28 Mitsubishi Electric Corp 位相同期ル−プ回路
JPS63136825A (ja) * 1986-11-28 1988-06-09 Mitsubishi Electric Corp 同期・非同期状態検出カウンタ−付位相ロツクル−プ
JP3275222B2 (ja) * 1994-03-04 2002-04-15 富士通株式会社 位相同期発振器
JP3481148B2 (ja) * 1998-10-15 2003-12-22 富士通株式会社 Dll回路を有する集積回路装置
JPH11205102A (ja) * 1998-01-13 1999-07-30 Mitsubishi Electric Corp 遅延同期回路
US6239634B1 (en) * 1999-05-19 2001-05-29 Parthus Technologies Apparatus and method for ensuring the correct start-up and locking of a delay locked loop
JP3808670B2 (ja) 1999-08-19 2006-08-16 富士通株式会社 半導体集積回路
JP2002064371A (ja) 2000-08-14 2002-02-28 Nec Corp 位相周波数比較器および位相周波数比較器の初期化方法
US6504408B1 (en) * 2001-07-09 2003-01-07 Broadcom Corporation Method and apparatus to ensure DLL locking at minimum delay
US6628154B2 (en) * 2001-07-31 2003-09-30 Cypress Semiconductor Corp. Digitally controlled analog delay locked loop (DLL)
US6683478B2 (en) 2001-11-13 2004-01-27 Samsung Electronics Co., Ltd. Apparatus for ensuring correct start-up and phase locking of delay locked loop
TW558872B (en) * 2002-05-21 2003-10-21 Via Tech Inc Delay-locked loop device and method for generating clock signal
US7477716B2 (en) 2003-06-25 2009-01-13 Mosaid Technologies, Inc. Start up circuit for delay locked loop
US6867627B1 (en) * 2003-09-16 2005-03-15 Integrated Device Technology, Inc. Delay-locked loop (DLL) integrated circuits having high bandwidth and reliable locking characteristics
US7002384B1 (en) * 2004-01-16 2006-02-21 Altera Corporation Loop circuitry with low-pass noise filter
KR100605588B1 (ko) 2004-03-05 2006-07-28 주식회사 하이닉스반도체 반도체 기억 소자에서의 지연 고정 루프 및 그의 클럭록킹 방법
JP3993860B2 (ja) 2004-04-19 2007-10-17 富士通株式会社 Dll回路
KR100537202B1 (ko) * 2004-05-06 2005-12-16 주식회사 하이닉스반도체 지연고정루프의 지연고정상태 정보의 이용이 가능한반도체 소자
US7355464B2 (en) * 2005-05-09 2008-04-08 Micron Technology, Inc. Apparatus and method for controlling a delay- or phase-locked loop as a function of loop frequency

Also Published As

Publication number Publication date
US7482850B2 (en) 2009-01-27
US20090134924A1 (en) 2009-05-28
US7675334B2 (en) 2010-03-09
JP2007243877A (ja) 2007-09-20
TW200737726A (en) 2007-10-01
CN101039108B (zh) 2010-09-08
US20070210842A1 (en) 2007-09-13
EP1835623A1 (en) 2007-09-19
KR20070093322A (ko) 2007-09-18
TWI399038B (zh) 2013-06-11
EP1835623B1 (en) 2013-08-14
CN101039108A (zh) 2007-09-19

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