JP5110776B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 46
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 238000005468 ion implantation Methods 0.000 claims description 36
- 239000000758 substrate Substances 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 17
- 239000012535 impurity Substances 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 239000011229 interlayer Substances 0.000 claims 2
- 239000010410 layer Substances 0.000 claims 2
- 230000015556 catabolic process Effects 0.000 description 11
- 238000009792 diffusion process Methods 0.000 description 10
- 150000002500 ions Chemical class 0.000 description 9
- 235000004522 Pentaglottis sempervirens Nutrition 0.000 description 7
- 240000004050 Pentaglottis sempervirens Species 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 3
- 210000000746 body region Anatomy 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
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Description
(1)1つ目の課題を示す。図3は図2のソース領域001もしくはドレイン領域002のみを取出した鳥瞰図である。ここでゲート酸化膜004とゲート電極003は図示していない。図3のソース領域001もしくはドレイン領域002において、点線で表したトレンチ壁に接した極表面の色の濃い部分がチャネル部と接する部分020である。このチャネル部と接する部分020はトレンチ壁に接触しているソース領域001もしくはドレイン領域002の極表面全てに存在する。つまり、図2の構造においてソース領域001もしくはドレイン領域002と前記チャネル部の接触面積は寸法d1、w1、l 2の長さによって決定される。前記接触面積が小さい場合、その部分が図4(d)の電流019が示すようにボトルネックとなり(電流密度がソース領域及びドレイン領域で密となり)、オン抵抗低減を阻害する。前記接触面積を大きくするには寸法d1、w1、l2の長さを長く取ればよい。まず、寸法d1について考えると、ソース領域及びドレイン領域を通常のイオン注入によって形成した場合のソース領域001及びドレイン領域002の深さである寸法d1は一般に数千Aと浅く、深くするには限界がある。前記トレンチの凸部幅を変えずに前記トレンチの凹部幅である寸法w1を長くすると、単位平面積あたりの前記トレンチ数が減少し垂直な接触面積が減少することとなり、ゲート幅が短くなるため寸法w1を長くすることができない。
(2)2つ目の課題は、トレンチ深さに限界があることである。トレンチ深さを深くすることで単位平面積あたりのゲート幅を更に増加させる事が可能であるが、それはウェル領域005内に限った話で、一般的方法で作成するウェル領域005の深さには限界があるため、ウェル領域005の深さ以上にトレンチを深くすることはできない。仮にウェル領域005の深さ以上にトレンチを深くすると、基板に電流が漏れてしまう。
(2)DDD構造を有する(1)に記載の半導体装置とした。
(3)LDMOS構造を有する(1)に記載の半導体装置とした。
(4)前記第1トレンチ領域の凸部の幅が1000A程度の(1)から(3)に記載のいずれかの半導体装置とした。
(5)ツインウェル技術を併合した(1)から(4)に記載のいずれかの半導体装置とした。
(6)導電型を反転した(1)から(5)に記載のいずれかの半導体装置とした。
(7)(1)から(6)に記載の半導体装置において、前記トレンチ領域形成後に多方向からによる斜めイオン注入によって前記ウェル領域を形成する半導体装置の製造法とした。
(8)(1)から(6)に記載の半導体装置において、前記トレンチ領域形成後に多方向からによる斜めイオン注入によって前記ソース領域と前記ドレイン領域を形成する半導体装置の製造法とした。
(9)(1)から(6)に記載の半導体装置において、前記半導体基板の表面にイオン注入によって第2導電型半導体領域を作成する工程と、前記半導体基板の表面に半導体をエピタキシャル成長させる工程と、前記のエピタキシャル成長させた半導体表面にイオン注入によって第2導電型半導体領域を作成する工程により、前記ウェル領域を作成する工程を有する半導体装置の製造法とした。
更に、本発明によれば、DDDやLDMOSなどの構造を採用するといった従来技術との併合が可能であるため、容易に耐圧の向上が図れる。
更に、本発明によれば、ツインウェル技術を利用することにより、1チップで高駆動能力を有するCMOS構造を作成することも、IC混載も容易に可能となる。
更に、本発明によれば、トレンチ形成直後に多方向からの斜めイオン注入によってソース領域およびドレイン領域を形成するため、ウェル領域は凹部底面よりも深く形成される。従って、トレンチ形状を作成する前にソース領域およびドレイン領域を作る手法よりトレンチ深さを深くすることができ、チャネルとの接触面積が増加しトランジスタのオン抵抗が低減する。
次に、図4(f)に示すように、前期半導体基板の表面全体を覆うように電極膜を堆積させた後、ソース領域001及びドレイン領域002電気的に接続する電極膜010を残し、他の前記電極膜をエッチングで除去する。
002 ドレイン領域
003 ゲート電極
004 ゲート絶縁膜
005 ウェル領域
006 半導体基板
007 凸部
008 凹部
009 絶縁膜
010 電極膜
011 低濃度拡散領域
012 ボディ領域
013 第1トレンチ領域
014 第2トレンチ領域
015 第3トレンチ領域
016 イオン注入されたイオン
017 イオン注入の方向
018 エピタキシャル成長による半導体膜
019 電流
020 チャネル部と接している部分
Claims (3)
- 半導体基板に複数本のトレンチを形成する工程と、
前記複数本のトレンチを形成する工程のあとに、前記トレンチよりも深い第一導電型のウェル領域を形成する工程と、
前記ウェル領域を形成する工程のあとに、前記トレンチが形成する凹凸部の表面にゲート絶縁膜を設ける工程と、
前記ゲート絶縁膜を介して前記トレンチ内部を埋め込むとともに、前記トレンチ両端を除く前記凹凸部において、前記ゲート絶縁膜上にゲート電極を設ける工程と、
前記ゲート電極を設ける工程のあとに、前記ゲート電極膜の下部を除く前記ウェル領域において、前記ウェル領域の深さより浅く、2つの第二導電型半導体層であるソース領域およびドレイン領域を設ける工程と、
前記ゲート電極膜と前記ソース領域および前記ドレイン領域を覆う層間絶縁膜を堆積する工程と、
前記ゲート電極膜が露出しないように前記ゲート電極膜の上部および側面以外の前記層間絶縁膜を除去し前記ソース領域およびドレイン領域を露出させる工程と、
前記露出したソース領域およびドレイン領域を覆うとともに、それらが接触しないように、電極膜を堆積させる工程と、
を有し、
前記ソース領域およびドレイン領域を設ける工程は、多方向からの斜めイオン注入によって前記ソース領域およびドレイン領域にある前記凹凸部をつないでいる側面にも第二導電型の不純物を拡散する工程である半導体装置の製造方法。 - 前記ウェル領域を形成する工程は、前記トレンチの形成後に多方向からの斜めイオン注入によって前記第一導電型のウェル領域を形成する工程である請求項1記載の半導体装置の製造方法。
- 前記ウェル領域を形成する工程は、前記半導体基板の表面にイオン注入によって第2導電型半導体領域を作成する工程と、前記半導体基板の表面に半導体をエピタキシャル成長させる工程と、前記のエピタキシャル成長させた半導体表面にイオン注入によって第2導電型半導体領域を作成する工程と、からなる請求項1記載の半導体装置の製造方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005144867A JP5110776B2 (ja) | 2004-07-01 | 2005-05-18 | 半導体装置の製造方法 |
US11/155,960 US7242058B2 (en) | 2004-07-01 | 2005-06-17 | Lateral semiconductor device using trench structure and method of manufacturing the same |
TW094120810A TWI380444B (en) | 2004-07-01 | 2005-06-22 | Lateral semiconductor device using trench structure and method of manufacturing the same |
KR1020050057911A KR101152451B1 (ko) | 2004-07-01 | 2005-06-30 | 트렌치 구조를 이용한 횡형 반도체 장치 및 그 제조 방법 |
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JP2004195887 | 2004-07-01 | ||
JP2004195887 | 2004-07-01 | ||
JP2005144867A JP5110776B2 (ja) | 2004-07-01 | 2005-05-18 | 半導体装置の製造方法 |
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JP2012193987A Division JP5486654B2 (ja) | 2004-07-01 | 2012-09-04 | 半導体装置 |
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JP (1) | JP5110776B2 (ja) |
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US20060071270A1 (en) * | 2004-09-29 | 2006-04-06 | Shibib Muhammed A | Metal-oxide-semiconductor device having trenched diffusion region and method of forming same |
EP1892750B1 (en) * | 2006-08-23 | 2012-11-28 | Imec | Method for doping a fin-based semiconductor device |
JP2008053468A (ja) * | 2006-08-24 | 2008-03-06 | Seiko Instruments Inc | トレンチ構造を利用した横型高駆動能力半導体装置 |
JP2008192985A (ja) | 2007-02-07 | 2008-08-21 | Seiko Instruments Inc | 半導体装置、及び半導体装置の製造方法 |
JP5165954B2 (ja) * | 2007-07-27 | 2013-03-21 | セイコーインスツル株式会社 | 半導体装置 |
JP5314949B2 (ja) * | 2007-07-27 | 2013-10-16 | セイコーインスツル株式会社 | 半導体装置の製造方法 |
US8236648B2 (en) * | 2007-07-27 | 2012-08-07 | Seiko Instruments Inc. | Trench MOS transistor and method of manufacturing the same |
JP5159365B2 (ja) * | 2008-02-26 | 2013-03-06 | セイコーインスツル株式会社 | 半導体装置およびその製造方法 |
JP5341639B2 (ja) | 2009-06-26 | 2013-11-13 | ルネサスエレクトロニクス株式会社 | 半導体装置および半導体装置の製造方法 |
JPWO2012099142A1 (ja) | 2011-01-18 | 2014-06-30 | 千寿製薬株式会社 | 保存効力を有するブロムフェナク水性液剤組成物 |
JP5486673B2 (ja) * | 2012-12-26 | 2014-05-07 | セイコーインスツル株式会社 | 半導体装置 |
US9997599B2 (en) * | 2013-10-07 | 2018-06-12 | Purdue Research Foundation | MOS-based power semiconductor device having increased current carrying area and method of fabricating same |
DE102014104589B4 (de) * | 2014-04-01 | 2017-01-26 | Infineon Technologies Ag | Halbleitervorrichtung und integrierte Schaltung |
US9601578B2 (en) * | 2014-10-10 | 2017-03-21 | Globalfoundries Inc. | Non-planar vertical dual source drift metal-oxide semiconductor (VDSMOS) |
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US4569701A (en) * | 1984-04-05 | 1986-02-11 | At&T Bell Laboratories | Technique for doping from a polysilicon transfer layer |
JPH02134871A (ja) * | 1988-11-15 | 1990-05-23 | Mitsubishi Electric Corp | 半導体装置 |
JP2994670B2 (ja) * | 1989-12-02 | 1999-12-27 | 忠弘 大見 | 半導体装置及びその製造方法 |
JPH04276662A (ja) * | 1991-03-05 | 1992-10-01 | Kawasaki Steel Corp | 半導体装置の製造方法 |
JP3017838B2 (ja) * | 1991-06-06 | 2000-03-13 | 株式会社東芝 | 半導体装置およびその製造方法 |
JPH05110083A (ja) * | 1991-10-15 | 1993-04-30 | Oki Electric Ind Co Ltd | 電界効果トランジスタ |
JP3311070B2 (ja) * | 1993-03-15 | 2002-08-05 | 株式会社東芝 | 半導体装置 |
JPH06302818A (ja) * | 1993-04-16 | 1994-10-28 | Kawasaki Steel Corp | 半導体装置 |
JPH08264764A (ja) * | 1995-03-22 | 1996-10-11 | Toshiba Corp | 半導体装置 |
JPH0923011A (ja) * | 1995-07-05 | 1997-01-21 | Hitachi Ltd | 半導体装置及びその製造方法 |
JP3405681B2 (ja) * | 1997-07-31 | 2003-05-12 | 株式会社東芝 | 半導体装置 |
DE19908809B4 (de) * | 1999-03-01 | 2007-02-01 | Infineon Technologies Ag | Verfahren zur Herstellung einer MOS-Transistorstruktur mit einstellbarer Schwellspannung |
US6461918B1 (en) * | 1999-12-20 | 2002-10-08 | Fairchild Semiconductor Corporation | Power MOS device with improved gate charge performance |
JP2002026311A (ja) * | 2000-07-04 | 2002-01-25 | Miyazaki Oki Electric Co Ltd | Soi型mos素子およびその製造方法 |
US6661050B2 (en) * | 2002-03-20 | 2003-12-09 | Taiwan Semiconductor Manufacturing Co., Ltd | Memory cell structure with trench capacitor and method for fabrication thereof |
JP3927111B2 (ja) * | 2002-10-31 | 2007-06-06 | 株式会社東芝 | 電力用半導体装置 |
US6861701B2 (en) * | 2003-03-05 | 2005-03-01 | Advanced Analogic Technologies, Inc. | Trench power MOSFET with planarized gate bus |
JP4829473B2 (ja) * | 2004-01-21 | 2011-12-07 | オンセミコンダクター・トレーディング・リミテッド | 絶縁ゲート型半導体装置およびその製造方法 |
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US20060001085A1 (en) | 2006-01-05 |
JP2006049826A (ja) | 2006-02-16 |
TWI380444B (en) | 2012-12-21 |
US7242058B2 (en) | 2007-07-10 |
KR20060049250A (ko) | 2006-05-18 |
TW200611409A (en) | 2006-04-01 |
KR101152451B1 (ko) | 2012-06-01 |
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