JP5047739B2 - デューティサイクル補正機能を有する遅延ロックループ回路およびその制御方法 - Google Patents

デューティサイクル補正機能を有する遅延ロックループ回路およびその制御方法 Download PDF

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Publication number
JP5047739B2
JP5047739B2 JP2007226719A JP2007226719A JP5047739B2 JP 5047739 B2 JP5047739 B2 JP 5047739B2 JP 2007226719 A JP2007226719 A JP 2007226719A JP 2007226719 A JP2007226719 A JP 2007226719A JP 5047739 B2 JP5047739 B2 JP 5047739B2
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JP
Japan
Prior art keywords
duty cycle
clock
cycle correction
delay
locked loop
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Expired - Fee Related
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JP2007226719A
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English (en)
Japanese (ja)
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JP2008199573A (ja
JP2008199573A5 (enExample
Inventor
勳 崔
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SK Hynix Inc
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SK Hynix Inc
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Publication of JP2008199573A publication Critical patent/JP2008199573A/ja
Publication of JP2008199573A5 publication Critical patent/JP2008199573A5/ja
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Expired - Fee Related legal-status Critical Current
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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
    • H03K5/1565—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern the output pulses having a constant duty cycle
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Dram (AREA)
JP2007226719A 2007-02-09 2007-08-31 デューティサイクル補正機能を有する遅延ロックループ回路およびその制御方法 Expired - Fee Related JP5047739B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2007-0014061 2007-02-09
KR1020070014061A KR100863001B1 (ko) 2007-02-09 2007-02-09 듀티 싸이클 보정 기능을 갖는 지연 고정 루프 회로 및 그제어방법

Publications (3)

Publication Number Publication Date
JP2008199573A JP2008199573A (ja) 2008-08-28
JP2008199573A5 JP2008199573A5 (enExample) 2010-09-30
JP5047739B2 true JP5047739B2 (ja) 2012-10-10

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JP2007226719A Expired - Fee Related JP5047739B2 (ja) 2007-02-09 2007-08-31 デューティサイクル補正機能を有する遅延ロックループ回路およびその制御方法

Country Status (3)

Country Link
US (1) US7701273B2 (enExample)
JP (1) JP5047739B2 (enExample)
KR (1) KR100863001B1 (enExample)

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KR100891300B1 (ko) * 2007-09-04 2009-04-06 주식회사 하이닉스반도체 반도체 장치 및 그 구동방법
US7733141B2 (en) * 2007-11-02 2010-06-08 Hynix Semiconductor Inc. Semiconductor device and operating method thereof
KR100933805B1 (ko) * 2008-06-30 2009-12-24 주식회사 하이닉스반도체 듀티비 보정회로 및 그를 포함하는 지연고정루프회로
KR101019985B1 (ko) * 2008-09-10 2011-03-11 주식회사 하이닉스반도체 디엘엘 회로 및 그의 제어 방법
KR101022674B1 (ko) * 2008-12-05 2011-03-22 주식회사 하이닉스반도체 지연고정루프회로 및 그 동작방법
KR101605459B1 (ko) 2009-02-02 2016-03-23 삼성전자 주식회사 지연 고정 루프 회로 및 그를 채용한 반도체 메모리 장치
KR101094932B1 (ko) * 2009-07-01 2011-12-15 주식회사 하이닉스반도체 지연고정루프회로
US7999589B2 (en) 2009-09-03 2011-08-16 Micron Technology, Inc. Circuits and methods for clock signal duty-cycle correction
KR101145316B1 (ko) * 2009-12-28 2012-05-14 에스케이하이닉스 주식회사 반도체 장치 및 그의 동작 방법
KR101046705B1 (ko) * 2010-02-25 2011-07-05 주식회사 하이닉스반도체 반도체 장치 및 그 동작방법
KR101083639B1 (ko) * 2010-03-29 2011-11-16 주식회사 하이닉스반도체 반도체 장치 및 그 동작 방법
KR101103070B1 (ko) * 2010-04-30 2012-01-06 주식회사 하이닉스반도체 클럭 신호 듀티 보정 회로
US8400200B1 (en) 2011-07-09 2013-03-19 Gsi Technology, Inc. Systems and methods including features of power supply noise reduction and/or power-saving for high speed delay lines
JP6783535B2 (ja) * 2016-03-24 2020-11-11 株式会社メガチップス クロック補正装置及びクロック補正方法
US10153758B2 (en) * 2016-04-20 2018-12-11 SK Hynix Inc. Efficient digital duty cycle adjusters
WO2020236209A1 (en) * 2019-05-22 2020-11-26 Adesto Technologies Corporation Pulse width signal overlap compensation techniques
CN110489362B (zh) * 2019-08-22 2022-08-23 江苏华存电子科技有限公司 eMMC校正输出入有效窗口自动调整方法、装置、存储介质
KR102816578B1 (ko) * 2020-08-14 2025-06-04 삼성전자주식회사 듀티 조절 회로, 이를 포함하는 지연 동기 루프 회로 및 반도체 메모리 장치
US11611334B2 (en) * 2020-11-24 2023-03-21 Mediatek Inc. Method and circuit for monitoring and controlling duty margin of a signal

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KR100578232B1 (ko) * 2003-10-30 2006-05-12 주식회사 하이닉스반도체 지연 고정 루프
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KR100711547B1 (ko) * 2005-08-29 2007-04-27 주식회사 하이닉스반도체 지연 고정 루프
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US7449930B2 (en) * 2005-09-29 2008-11-11 Hynix Semiconductor Inc. Delay locked loop circuit
KR100800144B1 (ko) * 2006-05-12 2008-02-01 주식회사 하이닉스반도체 지연 고정 루프 장치 및 지연 고정 방법

Also Published As

Publication number Publication date
JP2008199573A (ja) 2008-08-28
KR100863001B1 (ko) 2008-10-13
KR20080074667A (ko) 2008-08-13
US7701273B2 (en) 2010-04-20
US20080191757A1 (en) 2008-08-14

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