JP5037006B2 - 半導体メモリ装置のカラム選択線信号生成装置 - Google Patents

半導体メモリ装置のカラム選択線信号生成装置 Download PDF

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Publication number
JP5037006B2
JP5037006B2 JP2005359515A JP2005359515A JP5037006B2 JP 5037006 B2 JP5037006 B2 JP 5037006B2 JP 2005359515 A JP2005359515 A JP 2005359515A JP 2005359515 A JP2005359515 A JP 2005359515A JP 5037006 B2 JP5037006 B2 JP 5037006B2
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Japan
Prior art keywords
column selection
selection line
signal
command
clock cycle
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Expired - Fee Related
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JP2005359515A
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Japanese (ja)
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JP2006172702A (ja
JP2006172702A5 (enExample
Inventor
黄性民
李載雄
姜▲サン▼錫
辛忠善
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G11C7/1012—Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1069—I/O lines read out arrangements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/002—Isolation gates, i.e. gates coupling bit lines to the sense amplifier

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
JP2005359515A 2004-12-13 2005-12-13 半導体メモリ装置のカラム選択線信号生成装置 Expired - Fee Related JP5037006B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020040104713A KR100610018B1 (ko) 2004-12-13 2004-12-13 반도체 메모리 장치의 컬럼 선택선 신호 생성 장치
KR10-2004-0104713 2004-12-13

Publications (3)

Publication Number Publication Date
JP2006172702A JP2006172702A (ja) 2006-06-29
JP2006172702A5 JP2006172702A5 (enExample) 2008-11-27
JP5037006B2 true JP5037006B2 (ja) 2012-09-26

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JP2005359515A Expired - Fee Related JP5037006B2 (ja) 2004-12-13 2005-12-13 半導体メモリ装置のカラム選択線信号生成装置

Country Status (3)

Country Link
US (1) US7295488B2 (enExample)
JP (1) JP5037006B2 (enExample)
KR (1) KR100610018B1 (enExample)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100821573B1 (ko) * 2006-04-05 2008-04-15 주식회사 하이닉스반도체 반도체 메모리의 컬럼 선택신호 생성장치
DE102006029169B4 (de) * 2006-06-24 2009-03-26 Qimonda Ag Speicherbaustein mit veränderbarer Spaltenselektionsdauer
KR100868251B1 (ko) * 2007-03-22 2008-11-12 주식회사 하이닉스반도체 반도체 메모리장치
KR100852002B1 (ko) * 2007-05-14 2008-08-13 주식회사 하이닉스반도체 반도체 메모리 장치의 컬럼 선택신호의 펄스 폭 제어회로
KR100881134B1 (ko) * 2007-06-27 2009-02-02 주식회사 하이닉스반도체 컬럼 엑세스 제어 장치
KR100924347B1 (ko) * 2008-01-03 2009-10-30 주식회사 하이닉스반도체 컬럼 선택 신호 제어 장치 및 방법
KR100967112B1 (ko) * 2008-11-10 2010-07-05 주식회사 하이닉스반도체 출력 인에이블 신호 생성회로
KR100980061B1 (ko) * 2008-12-23 2010-09-03 주식회사 하이닉스반도체 제어신호 생성회로
KR101020290B1 (ko) 2009-01-12 2011-03-07 주식회사 하이닉스반도체 버스트모드 제어회로
KR101047003B1 (ko) * 2009-06-26 2011-07-06 주식회사 하이닉스반도체 프리차지신호 생성회로 및 반도체 메모리 장치
KR101052078B1 (ko) * 2010-02-26 2011-07-27 주식회사 하이닉스반도체 반도체 메모리 장치 및 그 동작 방법
US9563253B2 (en) 2013-03-12 2017-02-07 Intel Corporation Techniques for power saving on graphics-related workloads
US9715909B2 (en) * 2013-03-14 2017-07-25 Micron Technology, Inc. Apparatuses and methods for controlling data timing in a multi-memory system
KR102686058B1 (ko) * 2016-09-06 2024-07-17 에스케이하이닉스 주식회사 반도체장치
US11462261B2 (en) * 2019-10-10 2022-10-04 Micron Technology, Inc. Methods of activating input/output lines of memory devices, and related devices and systems
US11715503B2 (en) 2021-03-26 2023-08-01 Changxin Memory Technologies, Inc. Signal generation circuit and memory
CN116072170B (zh) 2021-11-03 2025-06-27 长鑫存储技术有限公司 存储器读写电路、存储器控制方法及电子设备
CN116072169B (zh) * 2021-11-03 2025-06-27 长鑫存储技术有限公司 存储器读写电路、存储器控制方法及电子设备
TWI849542B (zh) * 2022-10-20 2024-07-21 晶豪科技股份有限公司 適應性產生行選擇線訊號的方法及電路

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0157289B1 (ko) * 1995-11-13 1998-12-01 김광호 컬럼 선택 신호 제어회로
US6038176A (en) * 1997-12-10 2000-03-14 Winbond Electronics Corporation Presettable semiconductor memory device
JPH11306758A (ja) * 1998-04-27 1999-11-05 Matsushita Electric Ind Co Ltd 半導体記憶装置
JP2000021198A (ja) * 1998-06-30 2000-01-21 Mitsubishi Electric Corp 同期型半導体集積回路装置
JP2003059264A (ja) * 2001-08-08 2003-02-28 Hitachi Ltd 半導体記憶装置
US6972978B1 (en) * 2002-03-15 2005-12-06 Integrated Device Technology, Inc. Content addressable memory (CAM) devices with block select and pipelined virtual sector look-up control and methods of operating same
KR100416622B1 (ko) * 2002-04-27 2004-02-05 삼성전자주식회사 동기식 반도체 메모리장치의 컬럼 디코더 인에이블 타이밍제어방법 및 장치
ITMI20021540A1 (it) 2002-07-12 2004-01-12 St Microelectronics Srl Regolatore di tensione multifase di tipo buck
JP2004178729A (ja) * 2002-11-28 2004-06-24 Hitachi Ltd 半導体記憶装置

Also Published As

Publication number Publication date
KR20060066203A (ko) 2006-06-16
US7295488B2 (en) 2007-11-13
JP2006172702A (ja) 2006-06-29
US20060126421A1 (en) 2006-06-15
KR100610018B1 (ko) 2006-08-08

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