JP4977461B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 76
- 239000004065 semiconductor Substances 0.000 title claims description 150
- 239000000758 substrate Substances 0.000 claims abstract description 62
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 50
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 50
- 238000000034 method Methods 0.000 claims abstract description 38
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 37
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 37
- 230000008569 process Effects 0.000 claims abstract description 14
- 239000012535 impurity Substances 0.000 claims description 26
- 229910021332 silicide Inorganic materials 0.000 claims description 25
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 25
- 238000007667 floating Methods 0.000 claims description 24
- 239000003990 capacitor Substances 0.000 claims description 22
- 238000005530 etching Methods 0.000 claims description 19
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 9
- 238000000059 patterning Methods 0.000 claims description 8
- 238000005468 ion implantation Methods 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 35
- 125000006850 spacer group Chemical group 0.000 abstract description 15
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 296
- 230000002093 peripheral effect Effects 0.000 description 36
- 239000010410 layer Substances 0.000 description 31
- 238000005229 chemical vapour deposition Methods 0.000 description 17
- 229920002120 photoresistant polymer Polymers 0.000 description 14
- 239000007789 gas Substances 0.000 description 13
- 238000002955 isolation Methods 0.000 description 13
- 230000006870 function Effects 0.000 description 10
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 8
- 238000001312 dry etching Methods 0.000 description 8
- 229910052698 phosphorus Inorganic materials 0.000 description 8
- 239000011574 phosphorus Substances 0.000 description 8
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052785 arsenic Inorganic materials 0.000 description 7
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 7
- 229910052796 boron Inorganic materials 0.000 description 7
- 238000012936 correction and preventive action Methods 0.000 description 7
- 230000014759 maintenance of location Effects 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 239000010936 titanium Substances 0.000 description 7
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 5
- 238000005498 polishing Methods 0.000 description 5
- 230000008439 repair process Effects 0.000 description 5
- 238000004544 sputter deposition Methods 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 4
- 238000000354 decomposition reaction Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 239000002784 hot electron Substances 0.000 description 4
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 230000002950 deficient Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 101000741396 Chlamydia muridarum (strain MoPn / Nigg) Probable oxidoreductase TC_0900 Proteins 0.000 description 1
- 101000741399 Chlamydia pneumoniae Probable oxidoreductase CPn_0761/CP_1111/CPj0761/CpB0789 Proteins 0.000 description 1
- 101000741400 Chlamydia trachomatis (strain D/UW-3/Cx) Probable oxidoreductase CT_610 Proteins 0.000 description 1
- 229910019001 CoSi Inorganic materials 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
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Description
半導体基板上に形成された第1ゲート電極を有する不揮発性メモリセルを備え、
前記第1ゲート電極の側壁には第1絶縁膜が形成され、
前記第1ゲート電極上には第2絶縁膜が形成され、
前記第1絶縁膜上および前記第2絶縁膜の存在下で前記半導体基板上に堆積された第3絶縁膜を有し、
前記第3絶縁膜は、前記第1絶縁膜および前記第2絶縁膜とは異なるエッチング選択比を有するものである。
前記第1絶縁膜および前記第2絶縁膜は酸化シリコンを主成分とし、
前記第3絶縁膜は窒化シリコンを主成分とするものである。
(a)半導体基板上に第1導電性膜を形成する工程、
(b)前記第1導電性膜上に第2絶縁膜を形成する工程、
(c)前記第2絶縁膜および前記第1導電性膜をパターニングして前記第1導電性膜から前記第1ゲート電極を形成し、前記第2絶縁膜を前記第1ゲート電極上に残す工程、
(d)前記(c)工程後、前記第1ゲート電極および前記第2絶縁膜の側壁に第1絶縁膜を形成する工程、
(e)前記第1絶縁膜および前記第2絶縁膜の存在下で、前記半導体基板上に前記第1絶縁膜および前記第2絶縁膜とは異なるエッチング選択比を有する第3絶縁膜を形成する工程、
を含むものである。
前記第1絶縁膜および前記第2絶縁膜は酸化シリコンを主成分とし、
前記第3絶縁膜は窒化シリコンを主成分とするものである。
図1は、本実施の形態1の半導体装置が有する不揮発性メモリにおけるメモリセルの等価回路図であり、一点鎖線で囲んだ領域がメモリセルとなる。この回路においては、複数の不揮発性記憶素子PM1、PM2の浮遊ゲートをOR論理接続された複数の読み出しMISFETDM1、DM2のゲート電極として使用し、読み出し時に不揮発性記憶素子PM1、PM2のコントロールゲートcgを1.5Vとする。また、2つの不揮発性記憶素子PM1、PM2の浮遊ゲートは、読み出しMISFETDM1、DM2のゲート電極にそれぞれ直列接続されている。
次に、本実施の形態2の不揮発性メモリの構造について、図22〜図31を用いてその製造工程と共に説明する。本実施の形態2の不揮発性メモリのメモリセルの平面構造は、前記実施の形態1において図示したメモリセルの平面構造とほぼ同様の構造となるため、本実施の形態2においてはその平面構造の図示は省略する。図22〜図31で示す各断面図において、符号Bを付した部分は前記実施の形態1で用いた各平面図B−B線に沿ったメモリセルの断面、符号Cを付した部分は対応する前記実施の形態1で用いた各平面図C−C線に沿ったメモリセルの断面、その他の部分は周辺回路領域の一部の断面を示している。また、図22〜図31中に示す周辺回路領域では、周辺回路を構成するnチャネル型MISFET、pチャネル型MISFETおよび抵抗素子が形成される。すなわち、図22を例に説明すると、図22の左から、それぞれ各平面図B−B線に沿ったメモリセルの断面図、各平面図C−C線に沿ったメモリセルの断面図、nチャネル型MISFET、pチャネル型MISFETが形成される周辺回路領域、抵抗素子形成領域が示されている。
次に、本実施の形態3の不揮発性メモリの構造について、図32〜図52を用いてその製造工程と共に説明する。図32〜図52で示す各断面図において、符号Aを付した部分は対応する平面図A−A線に沿ったメモリセルの断面、符号Bを付した部分は対応する平面図B−B線に沿ったメモリセルの断面、その他の部分は周辺回路領域の一部の断面を示している。また、図32〜図52中に示す周辺回路領域では、周辺回路を構成するnチャネル型MISFET、容量素子および抵抗素子が形成される。なお、周辺回路を構成するpチャネル型MISFETについては、nチャネル型MISFETと導電型が逆になるだけで構造についてはほぼ同一となることから、本実施の形態3においては、各断面図においてそのpチャネル型MISFETが形成される領域の図示は省略する。
Claims (5)
- 第1ゲート電極を有する不揮発性メモリセルを備えた半導体装置の製造方法
であって、
(a)半導体基板上に第1導電性膜を形成する工程、
(b)前記第1導電性膜上に第2絶縁膜を形成する工程、
(c)前記第2絶縁膜および前記第1導電性膜をパターニングして前記第1導電性膜から前記第1ゲート電極を形成し、前記第2絶縁膜を前記第1ゲート電極上に残す工程、
(d)前記(c)工程後、前記第1ゲート電極および前記第2絶縁膜の側壁に第1絶縁膜を形成する工程、
(e)前記第1絶縁膜および前記第2絶縁膜の存在下で、前記半導体基板上に前記第1絶縁膜および前記第2絶縁膜とは異なるエッチング選択比を有する第3絶縁膜を形成する工程、
を含み、
前記(b)工程は、
(b1)前記第2絶縁膜をパターニングし、MISFETが形成される第1領域の前記第2絶縁膜を除去する工程、
(b2)前記(b1)工程後、前記半導体基板上に第5絶縁膜を形成する工程、
を含み、
前記(c)工程は、
(c1)前記第5絶縁膜、前記第2絶縁膜および前記第1導電性膜をパターニングして前記第1導電性膜から前記第1ゲート電極および前記MISFETの第2ゲート電極を形成し、前記第5絶縁膜を前記第1ゲート電極および前記第2ゲート電極上に残す工程、
を含み、
前記(d)工程は、
(d1)前記半導体基板上に前記第1絶縁膜を堆積する工程、
(d2)前記第1絶縁膜および前記第5絶縁膜を異方的にエッチングし、前記第1絶縁膜を前記第1ゲート電極、前記第2ゲート電極および前記第2絶縁膜の側壁に残し、前記第2ゲート電極上の前記第5絶縁膜を除去する工程、
を含み、
前記第1ゲート電極は、前記不揮発性メモリセルの浮遊ゲート電極を構成し、
前記不揮発性メモリセルは、前記浮遊ゲート電極の蓄積電荷量に応じてデータを記憶し、
前記第1絶縁膜及び第2絶縁膜は酸化シリコンを主成分とし、
前記第3絶縁膜は、SiH4とN2との混合ガスを用いたプラズマCVD法により形成された窒化シリコンを主成分とすることを特徴とする半導体装置の製造方法。 - 半導体基板の第1領域に第1ゲート電極を有する不揮発性メモリセルおよび前記半導体基板の第2領域に抵抗素子を備えた半導体装置の製造方法であって、
(a)前記第1領域および第2領域上に第1導電性膜を形成する工程、
(b)前記第1導電性膜上に第6絶縁膜を形成する工程、
(c)前記第6絶縁膜および前記第1導電性膜をパターニングして、前記第1領域に前記第1ゲート電極を形成し、前記第6絶縁膜を前記第1ゲート電極上に残す工程であって、前記第2領域に前記抵抗素子を形成し、前記第6絶縁膜を前記抵抗素子上に残す工程、
(d)前記(c)工程後、前記半導体基板上に第1絶縁膜を堆積する工程、
(e)前記第1絶縁膜および前記第6絶縁膜を異方的にエッチングし、前記第1絶縁膜を前記第1ゲート電極および前記抵抗素子の側壁に残し、前記第6絶縁膜を除去する工程、
(f)前記半導体基板に不純物をイオン注入し、前記第1領域にソースあるいはドレインとなる第1半導体領域を形成する工程、
(g)前記(f)工程後、前記半導体基板上に第2絶縁膜を形成する工程、
(h)前記第2絶縁膜をパターニングし、前記第1領域の前記第1ゲート電極上および前記第1絶縁膜上に前記第2絶縁膜を残す工程であって、前記第2領域の前記抵抗素子上の一部を露出させる工程、
(i)第1半導体領域および前記抵抗素子上の露出した領域に、シリサイド層を形成する工程、
(j)前記半導体基板上に前記第1絶縁膜および前記第2絶縁膜とは異なるエッチング選択比を有する第3絶縁膜を形成する工程、
を含み、
前記第1ゲート電極は、前記不揮発性メモリセルの浮遊ゲート電極を構成し、
前記不揮発性メモリセルは、前記浮遊ゲート電極の蓄積電荷量に応じてデータを記憶し、
前記第1絶縁膜及び第2絶縁膜は酸化シリコンを主成分とし、
前記第3絶縁膜は、SiH4とN2との混合ガスを用いたプラズマCVD法により形成された窒化シリコンを主成分とすることを特徴とする半導体装置の製造方法。 - 第1ゲート電極および第3ゲート電極を有する不揮発性メモリセルと、第1容量電極および第2容量電極を有する容量素子とを備えた半導体装置の製造方法であって、
(a)半導体基板上に第1導電性膜を形成する工程、
(b)前記第1導電性膜上に第4絶縁膜を形成する工程、
(c)前記第4絶縁膜および前記第1導電性膜をパターニングして前記第1導電性膜から前記第1容量電極を形成し、前記第4絶縁膜を前記第1容量電極上に残す工程、
(d)前記(c)工程後、前記半導体基板上に第2導電性膜を形成する工程、
(e)前記第2導電性膜上に第2絶縁膜を形成する工程、
(f)前記第2絶縁膜および前記第2導電性膜をパターニングして前記第2導電性膜から前記第3ゲート電極および第2容量電極を形成し、前記第2絶縁膜を前記第3ゲート電極上および第2容量電極上に残す工程、
(g)前記(f)工程後、前記第1容量電極以外の前記第1導電性膜および前記第1容量電極上以外の前記第4絶縁膜をパターニングし、前記第1導電性膜から前記第1ゲート電極を形成し、前記第4絶縁膜を前記第1ゲート電極上に残す工程、
(h)前記(g)工程後、前記第1ゲート電極、前記第3ゲート電極、前記第1容量電極および前記第2容量電極の側壁に第1絶縁膜を形成する工程、
(i)前記第1絶縁膜および前記第2絶縁膜の存在下で、前記半導体基板上に前記第1絶縁膜および前記第2絶縁膜とは異なるエッチング選択比を有する第3絶縁膜を形成する工程、
を含み、
前記第1ゲート電極は、前記不揮発性メモリセルの浮遊ゲート電極を構成し、
前記不揮発性メモリセルは、前記浮遊ゲート電極の蓄積電荷量に応じてデータを記憶し、
前記第1絶縁膜及び第2絶縁膜は酸化シリコンを主成分とし、
前記第3絶縁膜は、SiH4とN2との混合ガスを用いたプラズマCVD法により形成された窒化シリコンを主成分とすることを特徴とする半導体装置の製造方法。 - 請求項3記載の半導体装置の製造方法において、
前記(f)工程時には、前記第2導電性膜からMISFETの第2ゲート電極が形成されることを特徴とする半導体装置の製造方法。 - 請求項3記載の半導体装置の製造方法において、
前記(f)工程時には、前記第2導電性膜から抵抗素子が形成されることを特徴とする半導体装置の製造方法。
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