CN108666312B - 具有嵌入闪存存储器的动态随机存储器元件及其制作方法 - Google Patents

具有嵌入闪存存储器的动态随机存储器元件及其制作方法 Download PDF

Info

Publication number
CN108666312B
CN108666312B CN201710201701.5A CN201710201701A CN108666312B CN 108666312 B CN108666312 B CN 108666312B CN 201710201701 A CN201710201701 A CN 201710201701A CN 108666312 B CN108666312 B CN 108666312B
Authority
CN
China
Prior art keywords
region
layer
transistor
forming
flash memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201710201701.5A
Other languages
English (en)
Other versions
CN108666312A (zh
Inventor
永井享浩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
Original Assignee
Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujian Jinhua Integrated Circuit Co Ltd, United Microelectronics Corp filed Critical Fujian Jinhua Integrated Circuit Co Ltd
Priority to CN201710201701.5A priority Critical patent/CN108666312B/zh
Priority to US15/868,955 priority patent/US10373683B2/en
Publication of CN108666312A publication Critical patent/CN108666312A/zh
Priority to US16/438,485 priority patent/US10529423B2/en
Application granted granted Critical
Publication of CN108666312B publication Critical patent/CN108666312B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
    • G11C14/0009—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a DRAM cell
    • G11C14/0018—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a DRAM cell whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G11C29/789—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using non-volatile cells or latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/816—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for an application-specific layout
    • G11C29/824—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for an application-specific layout for synchronous memories
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2229/00—Indexing scheme relating to checking stores for correct operation, subsequent repair or testing stores during standby or offline operation
    • G11C2229/70—Indexing scheme relating to G11C29/70, for implementation aspects of redundancy repair
    • G11C2229/72—Location of redundancy information
    • G11C2229/723—Redundancy information stored in a part of the memory core to be repaired
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Semiconductor Memories (AREA)

Abstract

本发明公开一种具有嵌入闪存存储器的动态随机存储器元件及其制作方法，包含有一半导体基底，具有一DRAM阵列区及一周边区，其中周边区包含一嵌入闪存存储器形成区及一第一晶体管形成区。多个DRAM存储单元，设于DRAM阵列区内。一闪存存储器，设于嵌入闪存存储器形成区内，其中闪存存储器包含一ONO存储结构及一闪存存储器栅极结构。一第一晶体管，设于第一晶体管形成区内。

Description

具有嵌入闪存存储器的动态随机存储器元件及其制作方法
技术领域
本发明涉及一种半导体元件及其制作方法，特别是涉及一种具有嵌入闪存存储器的动态随机存储器元件及其制作方法。
背景技术
已知，为了进行芯片修复，动态随机存取存储器芯片中常设有冗置的电熔丝(eFuse)或激光熔丝(Laser Fuse)。
然而，冗置的电熔丝或激光熔丝十分占据芯片面积，且无重复写入功能。此外，激光熔丝的体积虽然比电熔丝小，但是需要额外的高压电路设计。
因此，该技术领域仍需要一种尺寸更加微缩的冗置嵌入元件，能提供芯片修复或测试功能，具有高可靠度且可重复写入，且能与动态随机存取存储器元件的制作工艺相容。
发明内容
本发明的主要目的在于提供一种具有嵌入闪存存储器的动态随机存储器元件及其制作方法，以解决上述现有技术的不足与缺点。
根据本发明一实施例，提供一种具有嵌入闪存存储器的动态随机存储器元件的制作方法。首先提供一半导体基底，具有一动态随机存储器(DRAM)阵列区及一周边区，其中该周边区包含一嵌入闪存存储器形成区及一第一晶体管形成区。于该DRAM阵列区及该周边区上形成至少一氧化硅-氮化硅-氧化硅(ONO)层。
图案化该ONO层，以于该嵌入闪存存储器形成区上形成一ONO存储结构，并显露出该第一晶体管形成区内的该半导体基底。在该第一晶体管形成区内的该半导体基底上形成一第一栅极氧化层。在该DRAM阵列区及该周边区上全面沉积一第一栅极导电层。
对该DRAM阵列区进行一接触洞蚀刻制作工艺，蚀穿该第一栅极导电层、该ONO层，及部分该半导体基底，以形成一接触洞。在该DRAM阵列区及该周边区上全面沉积一第二栅极导电层，且使该第二栅极导电层填入该接触洞，以形成一接触结构。
在该第二栅极导电层上形成一金属层。图案化该金属层及该第一、第二栅极导电层，在该嵌入闪存存储器形成区内的该ONO存储结构上形成一闪存存储器栅极结构、在该第一晶体管形成区内形成一第一晶体管栅极结构，并于该DRAM阵列区形成至少一位线。
根据本发明另一实施例，提供一种具有嵌入闪存存储器的动态随机存储器元件，包含有一半导体基底，具有一动态随机存储器(DRAM)阵列区及一周边区，其中该周边区包含一嵌入闪存存储器形成区及一第一晶体管形成区。
多个DRAM存储单元，设于该DRAM阵列区内；一闪存存储器，设于该嵌入闪存存储器形成区内，其中该闪存存储器包含一ONO存储结构以及一闪存存储器栅极结构。一第一晶体管，设于该第一晶体管形成区内。
为让本发明上述目的、特征及优点能更明显易懂，下文特举优选实施方式，并配合所附的附图，作详细说明如下。然而优选实施方式与附图仅供参考与说明用，并非用来对本发明加以限制者。
附图说明
图1至图7为本发明实施例所绘示的具有嵌入闪存存储器的动态随机存储器元件的制作方法的示意图。
主要元件符号说明
11 DRAM存储单元
12 闪存存储器
13 第一晶体管
14 第二晶体管
22 沟槽绝缘结构
30 氧化硅-氮化硅-氧化硅(ONO)层
30a ONO存储结构
42 第一栅极氧化层
44 第二栅极氧化层
50 第一栅极导电层
52 第二栅极导电层
60 金属层
100 半导体基底
101 动态随机存储器(DRAM)阵列区(动态随机存取存储器阵列区)
102 周边区
110 接触洞
111 埋入字符线
150 接触结构
161、162、163 间隙壁
171、172、173 掺杂区
210 介电层
220 存储节点接触洞
AA1 嵌入闪存存储器形成区
AA2 第一晶体管形成区
AA3 第二晶体管形成区
BL 位线
FG 闪存存储器栅极结构
TG1 第一晶体管栅极结构
TG2 第二晶体管栅极结构
SC 存储节点接触
C1、C2 电容结构
具体实施方式
接下来的详细叙述是参照相关附图所示内容，用来说明可依据本发明具体实行的实施例。这些实施例已提供足够的细节，可使本领域技术人员充分了解并具体实行本发明。在不悖离本发明的范围内，仍可做结构或电性上的修改，并应用在其他实施例上。
因此，以下详细描述并非用来对本发明加以限制。本发明涵盖的范围由其权利要求界定。与本发明权利要求具均等意义者，也应属本发明涵盖的范围。
请参阅图1至图7，其为依据本发明实施例所绘示的具有嵌入闪存存储器的动态随机存储器存储器元件的制作方法。根据本发明实施例，所述嵌入闪存存储器为硅-氧化硅-氮化硅-氧化硅-硅(SONOS)型闪存存储器元件。
如图1所示，首先提供一半导体基底100，其中半导体基底100可以例如是硅基底、含硅基底(例如SiC)、三五族基底(例如GaN)、三五族覆硅基底(例如GaN-on-silicon)、石墨烯覆硅基底(graphene-on-silicon)、硅覆绝缘(silicon-on-insulator，SOI)基底、含外延层的基底或其他合适的半导体基底等，但不限于此。
根据本发明实施例，半导体基底100具有一动态随机存储器(DRAM)阵列区101及一周边区102，其中周边区102内还包含一嵌入闪存存储器形成区(或第一主动区域)AA1、一第一晶体管形成区(或第二主动区域)AA2，及一第二晶体管形成区(或第三主动区域)AA3。周边区102内还包含一沟槽绝缘结构22，将嵌入闪存存储器形成区AA1、第一晶体管形成区AA2及第二晶体管形成区AA3彼此电性绝缘隔离。
根据本发明实施例，在DRAM阵列区101中已形成有多条埋入字符线(buried wordline)111。由于埋入字符线111的做法为周知技术，故其细节不另赘述。在完成埋入字符线111的制作后，此时，半导体基底100具有一平坦表面。
如图2所示，接着于DRAM阵列区101及周边区102上全面形成至少一氧化硅-氮化硅-氧化硅(ONO)层30。根据本发明实施例，ONO层30在后续进行位线蚀刻过程中，主要用来作为一蚀刻停止层。
如图3所示，接着利用光刻及蚀刻制作工艺图案化ONO层30，以于嵌入闪存存储器形成区AA1上形成一ONO存储结构30a，并显露出第一晶体管形成区AA2及第二晶体管形成区AA3内的半导体基底的上表面。换言之，在此步骤中，除了DRAM阵列区101及嵌入闪存存储器形成区AA1以外，周边区102上其余区域的ONO层30均被去除。
然后，在第一晶体管形成区AA2内的半导体基底100上形成一第一栅极氧化层42，再于第二晶体管形成区AA3内的半导体基底100上形成一第二栅极氧化层44，其中第一栅极氧化层42的厚度大于第二栅极氧化层44的厚度。
接下来，在DRAM阵列区101及周边区102上全面沉积一第一栅极导电层50。根据本发明实施例，第一栅极导电层50包含多晶硅，但不限于此。
如图4所示，接着对DRAM阵列区101进行一接触洞蚀刻制作工艺，利用光刻及蚀刻制作工艺，蚀穿第一栅极导电层50、ONO层30，及部分的半导体基底100，以形成一接触洞110。根据本发明实施例，接触洞110位于两条相邻的埋入字符线111之间。
如图5所示，在完成DRAM阵列区101内的接触洞蚀刻制作工艺后，接着于DRAM阵列区101及周边区102上全面沉积一第二栅极导电层52，且使第二栅极导电层52填入接触洞110，以形成一接触结构150。根据本发明实施例，第二栅极导电层52包含多晶硅，但不限于此。
根据本发明实施例，接着，可以选择回蚀刻第二栅极导电层52，移除部分的第二栅极导电层52。
如图6所示，接着于第一栅极导电层50及第二栅极导电层52上形成一金属层60。根据本发明实施例，金属层60包含钨，但不限于此。
随后，以光刻及蚀刻制作工艺图案化金属层60及第一栅极导电层50、第二栅极导电层52，在嵌入闪存存储器形成区AA1内的ONO存储结构30a上形成一闪存存储器栅极结构FG、在第一晶体管形成区AA2内形成一第一晶体管栅极结构TG1，在第二晶体管形成区AA3内形成一第二晶体管栅极结构TG2。
如图7所示，接着于闪存存储器栅极结构FG、第一晶体管栅极结构TG1，及第二晶体管栅极结构TG2上形成间隙壁161、162、163。再以离子注入制作工艺分别于闪存存储器栅极结构FG、第一晶体管栅极结构TG1，及第二晶体管栅极结构TG2两侧的半导体基底100中形成掺杂区171、172、173，作为晶体管的漏极或源极，如此于嵌入闪存存储器形成区AA1内形成一闪存存储器12、在第一晶体管形成区AA2内形成一第一晶体管13，在第二晶体管形成区AA3内形成一第二晶体管14。
接着，以光刻及蚀刻制作工艺于DRAM阵列区101图案化金属层60及第一栅极导电层50、第二栅极导电层52，形成一位线BL。DRAM阵列区101内的ONO层30于形成位线BL的过程中是作为一蚀刻停止层。
接着，在半导体基底100上全面沉积一介电层210，覆盖住DRAM阵列区101及闪存存储器栅极结构FG、第一晶体管栅极结构TG1，及第二晶体管栅极结构TG2。
接着，以光刻及蚀刻制作工艺于DRAM阵列区101中形成存储节点接触洞220，再于存储节点接触洞220内形成存储节点接触(SC)结构。
最后，在存储节点接触结构上形成电容结构C1及C2，如此于DRAM阵列区101内形成多个DRAM存储单元11(图中仅显示两个DRAM存储单元)。
如图7所示，本发明具有嵌入闪存存储器的动态随机存储器，其结构上特征在于：半导体基底100上具有DRAM阵列区101及周边区102，其中周边区102包含嵌入闪存存储器形成区AA1、第一晶体管形成区AA2、第二晶体管形成区AA3。在DRAM阵列区101内设有多个DRAM存储单元11。
在嵌入闪存存储器形成区AA1内设有一闪存存储器12，其中闪存存储器12包含ONO存储结构30a以及闪存存储器栅极结构FG，闪存存储器栅极结构FG包含多晶硅层50以及金属层60，金属层60包含钨。
在第一晶体管形成区AA2内，设有第一晶体管13。在第二晶体管形成区AA3内，设有第二晶体管14。第一晶体管13包含第一栅极氧化层42，第二晶体管14包含第二栅极氧化层44，其中第一栅极氧化层42的厚度大于第二栅极氧化层44的厚度。
以上所述仅为本发明之优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (8)

1.一种具有嵌入闪存存储器的动态随机存储器元件的制作方法，包含有：
提供一半导体基底，具有动态随机存储器(DRAM)阵列区及周边区，其中该周边区包含嵌入闪存存储器形成区及第一晶体管形成区；
在该DRAM阵列区及该周边区上形成至少一氧化硅-氮化硅-氧化硅(ONO)层；
图案化该ONO层，以于该嵌入闪存存储器形成区上形成一ONO存储结构，并显露出该第一晶体管形成区内的该半导体基底；
在该第一晶体管形成区内的该半导体基底上形成一第一栅极氧化层；
在该DRAM阵列区及该周边区上全面沉积一第一栅极导电层；
对该DRAM阵列区进行一接触洞蚀刻制作工艺，蚀穿该第一栅极导电层、该ONO层，及部分该半导体基底，以形成一接触洞；
在该DRAM阵列区及该周边区上全面沉积一第二栅极导电层，且使该第二栅极导电层填入该接触洞，以形成一接触结构；
在该第二栅极导电层上形成一金属层；以及
图案化该金属层及该第一、第二栅极导电层，在该嵌入闪存存储器形成区内的该ONO存储结构上形成一闪存存储器栅极结构、在该第一晶体管形成区内形成一第一晶体管栅极结构，并于该DRAM阵列区形成至少一位线。
2.如权利要求1所述的具有嵌入闪存存储器的动态随机存储器元件的制作方法，其中该周边区还包含第二晶体管形成区，该方法还包含以下步骤：
在该第二晶体管形成区内的该半导体基底上形成一第二栅极氧化层，其中该第一栅极氧化层的厚度大于该第二栅极氧化层的厚度。
3.如权利要求2所述的具有嵌入闪存存储器的动态随机存储器元件的制作方法，其中还包含以下步骤：
图案化该金属层及该栅极导电层，以于该第二晶体管形成区内形成一第二晶体管栅极结构。
4.如权利要求1所述的具有嵌入闪存存储器的动态随机存储器元件的制作方法，其中于该第二栅极导电层上形成一金属层之前，还包含以下步骤：
回蚀刻该第二栅极导电层。
5.如权利要求1所述的具有嵌入闪存存储器的动态随机存储器元件的制作方法，其中该第一栅极导电层包含多晶硅。
6.如权利要求1所述的具有嵌入闪存存储器的动态随机存储器元件的制作方法，其中该第二栅极导电层包含多晶硅。
7.如权利要求1所述的具有嵌入闪存存储器的动态随机存储器元件的制作方法，其中该金属层包含钨。
8.如权利要求1所述的具有嵌入闪存存储器的动态随机存储器元件的制作方法，其中该DRAM阵列区内的该ONO层于形成该位线的过程中是作为一蚀刻停止层。
CN201710201701.5A 2017-03-30 2017-03-30 具有嵌入闪存存储器的动态随机存储器元件及其制作方法 Active CN108666312B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201710201701.5A CN108666312B (zh) 2017-03-30 2017-03-30 具有嵌入闪存存储器的动态随机存储器元件及其制作方法
US15/868,955 US10373683B2 (en) 2017-03-30 2018-01-11 DRAM device with embedded flash memory for redundancy and fabrication method thereof
US16/438,485 US10529423B2 (en) 2017-03-30 2019-06-12 DRAM device with embedded flash memory for redundancy and fabrication method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710201701.5A CN108666312B (zh) 2017-03-30 2017-03-30 具有嵌入闪存存储器的动态随机存储器元件及其制作方法

Publications (2)

Publication Number Publication Date
CN108666312A CN108666312A (zh) 2018-10-16
CN108666312B true CN108666312B (zh) 2021-05-04

Family

ID=63669733

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710201701.5A Active CN108666312B (zh) 2017-03-30 2017-03-30 具有嵌入闪存存储器的动态随机存储器元件及其制作方法

Country Status (2)

Country Link
US (2) US10373683B2 (zh)
CN (1) CN108666312B (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110429084B (zh) * 2019-08-13 2022-04-26 德淮半导体有限公司 存储器的结构及其形成方法
US11468920B2 (en) * 2021-02-05 2022-10-11 Winbond Electronics Corp. Semiconductor connection structure and method for manufacturing the same
CN113113303B (zh) * 2021-04-02 2022-06-24 长鑫存储技术有限公司 半导体结构的制造方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100310255B1 (ko) * 1999-08-07 2001-09-29 박종섭 Ｍｍｌ반도체소자의 디램셀 및 플래시셀 형성방법
TW415045B (en) 1999-08-10 2000-12-11 United Microelectronics Corp Manufacture of embedded flash memory
JP3983996B2 (ja) * 2001-04-23 2007-09-26 株式会社ルネサステクノロジ 半導体集積回路装置
US6569729B1 (en) 2002-07-19 2003-05-27 Taiwan Semiconductor Manufacturing Company Method of fabricating three dimensional CMOSFET devices for an embedded DRAM application
JP2005044844A (ja) * 2003-07-23 2005-02-17 Toshiba Corp 不揮発性半導体記憶装置及びその製造方法
US6952366B2 (en) 2004-02-10 2005-10-04 Micron Technology, Inc. NROM flash memory cell with integrated DRAM
TW200826300A (en) * 2004-04-14 2008-06-16 Renesas Tech Corp Semiconductor device and manufacturing method thereof
US7495279B2 (en) * 2005-09-09 2009-02-24 Infineon Technologies Ag Embedded flash memory devices on SOI substrates and methods of manufacture thereof
KR101446331B1 (ko) * 2008-02-13 2014-10-02 삼성전자주식회사 반도체 소자의 제조 방법
TW201007930A (en) * 2008-08-07 2010-02-16 Nanya Technology Corp Dynamic random access memory structure, array thereof, and method of making the same
KR20110036312A (ko) * 2009-10-01 2011-04-07 삼성전자주식회사 반도체 소자 및 그 제조 방법
US8409950B1 (en) 2010-11-08 2013-04-02 Northrop Grumman Systems Corporation Method for integrating SONOS non-volatile memory into a sub-90 nm standard CMOS foundry process flow
US20130234252A1 (en) 2012-03-06 2013-09-12 United Microelectronics Corporation Integrated circuit and method for fabricating the same
CN103579312A (zh) * 2012-07-27 2014-02-12 上海华虹Nec电子有限公司 具有自对准接触孔与硅化物的器件及其制造方法
US8902663B1 (en) * 2013-03-11 2014-12-02 Monolithic 3D Inc. Method of maintaining a memory state
JP2016051822A (ja) * 2014-08-29 2016-04-11 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
KR20180072901A (ko) * 2016-12-21 2018-07-02 에스케이하이닉스 주식회사 반도체장치 및 그 제조 방법
US10062573B1 (en) * 2017-06-14 2018-08-28 Cypress Semiconductor Corporation Embedded SONOS with triple gate oxide and manufacturing method of the same

Also Published As

Publication number Publication date
CN108666312A (zh) 2018-10-16
US20180286481A1 (en) 2018-10-04
US10529423B2 (en) 2020-01-07
US10373683B2 (en) 2019-08-06
US20190295645A1 (en) 2019-09-26

Similar Documents

Publication Publication Date Title
US10833100B2 (en) Three-dimensional memory device including a deformation-resistant edge seal structure and methods for making the same
US11508614B2 (en) Method of forming semiconductor device having capped air gaps between buried bit lines and buried gate
US20130234242A1 (en) Semiconductor device with buried bit line and method for fabricating the same
KR20150110966A (ko) 반도체 장치 및 그 제조방법
KR20210080571A (ko) 메모리 어레이 및 메모리 어레이를 형성하는데 사용되는 방법
CN109494192B (zh) 半导体元件以及其制作方法
US10026741B2 (en) Logic-compatible memory cell manufacturing method and structure thereof
CN109390285B (zh) 接触结构及其制作方法
US9214470B2 (en) Non-volatile memory device with vertical memory cells and method for fabricating the same
US20090047777A1 (en) Semiconductor device and method of manufacturing the same
US10529423B2 (en) DRAM device with embedded flash memory for redundancy and fabrication method thereof
CN113437079A (zh) 存储器器件及其制造方法
CN106684088A (zh) 用于嵌入式闪存的无氮化物间隔件或氧化物间隔件
US20060286796A1 (en) Method of forming a contact in a flash memory device
US9059279B2 (en) Semiconductor device and method for forming the same
TWI575714B (zh) 三維記憶體
JP2016018899A (ja) 半導体装置およびその製造方法
CN112567515A (zh) 存储器结构及其形成方法
JP2008047863A (ja) 不揮発性メモリのウェルピックアップ構造を製造する方法
US20070196983A1 (en) Method of manufacturing non-volatile memory device
CN111987100B (zh) 半导体结构及其制造方法、存储器
US8148243B2 (en) Zero capacitor RAM with reliable drain voltage application and method for manufacturing the same
CN111863727A (zh) 半导体存储器件的制作方法
KR100903460B1 (ko) 갭필링층 형성단계를 갖는 메모리셀 제조방법 및 그 구조
KR20180099468A (ko) Nor형 플래시 메모리 및 그 제조 방법

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant