KR100310255B1 - Mml반도체소자의 디램셀 및 플래시셀 형성방법 - Google Patents
Mml반도체소자의 디램셀 및 플래시셀 형성방법 Download PDFInfo
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- KR100310255B1 KR100310255B1 KR1019990032414A KR19990032414A KR100310255B1 KR 100310255 B1 KR100310255 B1 KR 100310255B1 KR 1019990032414 A KR1019990032414 A KR 1019990032414A KR 19990032414 A KR19990032414 A KR 19990032414A KR 100310255 B1 KR100310255 B1 KR 100310255B1
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- South Korea
- Prior art keywords
- flash
- dram
- cell region
- forming
- cell
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000000034 method Methods 0.000 title claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 125000006850 spacer group Chemical group 0.000 claims description 12
- 239000003990 capacitor Substances 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 8
- 239000011229 interlayer Substances 0.000 claims description 6
- 230000000873 masking effect Effects 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 238000000206 photolithography Methods 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 230000000903 blocking effect Effects 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 19
- 239000010410 layer Substances 0.000 description 6
- 238000000151 deposition Methods 0.000 description 3
- 239000002131 composite material Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
Claims (2)
- 반도체기판 상에 디램셀영역과 플래시셀영역을 단입칩으로 형성하는 MML반도체소자에 있어서,상기 반도체기판 상에 필드산화막을 형성한 후, 디램셀 영역 및 플래시셀 영역에 각각 디램게이트 및 플래시플로팅게이트를 각각 형성하는 단계와;상기 결과물 상에 층간절연막을 적층한 후, 마스킹식각을 진행하여 소오스/드레인영역 및 디램게이트, 플래시플로팅게이트로 연결되는 디램콘택홀 및 플래시콘택홀을 각각 형성하는 단계와;상기 결과물 상에 스페이서막을 적층한 후, 플래시셀영역을 마스킹하여 차단하고, 디램셀영역을 식각하여 디램콘택홀의 내벽면에 콘택스페이서를 형성하는 단계와;상기 디램콘택홀 및 플래시콘택홀내에 배선물질을 몰입하여 사진식각공정으로 식각하여 디램셀 영역에는 디램비트라인을 형성하고, 플래시셀 영역에는 플래시커패시터 및 플래시콘트롤게이트전극을 형성하는 단계를 포함하는 것을 특징으로 하는 MML반도체소자의 디램셀 및 플래시셀 형성방법.
- 제 1 항에 있어서, 상기 스페이서막은, 실리콘산화막, 또는 실리콘질화막중 어느 하나를 사용하고, 플래시 셀 영역에서 플래시커패시터의 유전체막으로 사용되는 것을 특징으로 하는 MML반도체소자의 디램셀 및 플래시셀 형성방법.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019990032414A KR100310255B1 (ko) | 1999-08-07 | 1999-08-07 | Mml반도체소자의 디램셀 및 플래시셀 형성방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019990032414A KR100310255B1 (ko) | 1999-08-07 | 1999-08-07 | Mml반도체소자의 디램셀 및 플래시셀 형성방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20010017080A KR20010017080A (ko) | 2001-03-05 |
KR100310255B1 true KR100310255B1 (ko) | 2001-09-29 |
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Application Number | Title | Priority Date | Filing Date |
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KR1019990032414A KR100310255B1 (ko) | 1999-08-07 | 1999-08-07 | Mml반도체소자의 디램셀 및 플래시셀 형성방법 |
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KR (1) | KR100310255B1 (ko) |
Families Citing this family (1)
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CN108666312B (zh) * | 2017-03-30 | 2021-05-04 | 联华电子股份有限公司 | 具有嵌入闪存存储器的动态随机存储器元件及其制作方法 |
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1999
- 1999-08-07 KR KR1019990032414A patent/KR100310255B1/ko active IP Right Grant
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KR20010017080A (ko) | 2001-03-05 |
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