JP4950207B2 - 低ギャップフィルアスペクト比のフラッシュデバイスのための集積化フロー - Google Patents
低ギャップフィルアスペクト比のフラッシュデバイスのための集積化フロー Download PDFInfo
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- 229910052581 Si3N4 Inorganic materials 0.000 description 42
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 42
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
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- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- -1 Phosphorus ions Chemical class 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
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- 239000002002 slurry Substances 0.000 description 2
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- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
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- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
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- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
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- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
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- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
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Description
表1.注入シミュレーション結果:Ph+注入量:1.0E15atm/cm2
FG3 厚み=500A
エネルギー 濃度 酸化物深度
20KeV 8.3E17atm/cm3 280A
8.3E14atm/cm3 560A
表2:セルシミュレーション結果:
・FG1幅: 50nm 50nm
・FG2幅: 60nm 60nm
・EB量、D1: 60nm 50nm
・チャネルL: 51nm 51nm
→結合比 49.8% 46.7%
→総Yup 446mV 534mV
当該結果は、同一のFG1およびFG2寸法およびチャンネル長を有する2つのセルについてのものである。当該結果は、エッチバック量(D1)が60nmから50nm(600オングストロームから500オングストローム)へ減少すると、結合比は49.8%から46.7%へ減少し、隣接するセルの結合は上昇する場合を示す。「総Yup」とは、隣接するセル間のユーピン(Yupin)効果のことである。「ユーピン効果」は、隣接するセル間の望ましくない結合であって、これにより、あるフローティングゲートの電荷レベルが隣接するセルのしきい値電圧に悪影響を与えることを説明するために使用される用語である。この効果は、米国特許第5,867,429号(特許文献8)に詳細に記載されている。この特許は、その全体が本願明細書において参照により援用されている。よって、D1が60nmから50nmへ減少するとユーピン効果は増加し、結局はデバイス性能に悪影響を与えることがわかる。
Claims (9)
- 半導体基板上にメモリシステムを作る方法であって、
フローティングゲート構造を分離する複数の浅溝素子分離構造を形成するステップと、
複数の浅溝素子分離構造にイオンを注入するステップと、
浅溝素子分離構造のうちの注入イオンの濃度が高い部分が浅溝素子分離構造のうちの注入イオンの濃度が低い部分よりも高速にエッチングするように、複数の浅溝素子分離構造をエッチングするステップと、
注入イオンの濃度が最大濃度より低くかつエッチング深度が増加するにつれてエッチングレートが減少する深度において、複数の浅溝素子分離構造のエッチングを停止するステップと、
基板に渡ってイオンを注入する前に、複数の浅溝素子分離構造に重なる導電性ポリシリコン層を形成するステップと、
を含む方法。 - 請求項1記載の方法において、
導電性ポリシリコン層は、イオンを注入する前に平坦化される方法。 - 請求項1記載の方法において、
半導体基板は、メモリアレイと、周辺領域とを含み、個々の浅溝素子分離構造は、メモリアレイと周辺領域の両方に存在する方法。 - 請求項1記載の方法において、
ハードマスク部分が浅溝素子分離構造の位置を規定し、浅溝素子分離構造の位置を規定した後、ハードマスク部分は導電性フローティングゲート部分に置換される方法。 - メモリアレイ領域内のメモリアレイと、周辺領域内の周辺回路とを含む半導体基板上にメモリシステムを作る方法であって、
メモリアレイ領域と周辺領域の両方に複数の浅溝素子分離構造を形成するステップであって、周辺領域の浅溝素子分離構造がアレイ領域の浅溝素子分離構造よりも大きい、ステップと、
複数の浅溝素子分離構造を含む基板に渡ってイオンを注入するステップと、
複数の浅溝素子分離構造をエッチングするステップであって、浅溝素子分離構造のうちの注入イオンの濃度が高い部分をエッチングするエッチングが浅溝素子分離構造のうちの注入イオンの濃度が低い部分をエッチングするエッチングよりも高速にエッチングするステップと、
注入イオンの濃度が最大濃度より低くかつエッチング深度が増加するにつれてエッチングレートが減少する深度において、複数の浅溝素子分離構造のエッチングを停止するステップと、
基板に渡ってイオンを注入する前に、複数の浅溝素子分離構造に重なる導電性ポリシリコン層を形成するステップと、
を含む方法。 - 請求項5記載の方法において、
メモリアレイ領域にフローティングゲートを形成するステップであって、フローティングゲートはエッチングの前に浅溝素子分離構造によって分離され、フローティングゲート間の浅溝素子分離構造の上部がエッチングによって除去され、その後、浅溝素子分離構造の上部が除去されたフローティングゲート間に延びる誘電体層およびコントロールゲートが形成される、ステップをさらに含む方法。 - メモリデバイス用の基板を平坦化する方法であって、
複数の第1の導電部分の上面上に延びる、浅溝素子分離構造によって分離された複数の第1の導電部分を形成するステップと、
複数の第2の導電部分を形成するステップであって、個々の第2の導電部分は、第1の導電部分の上面に渡って部分的に延び、かつ浅溝素子分離構造に渡って部分的に延びる、ステップと、
その後、第2の導電部分を含む基板に渡って延びる導電層を形成するステップと、
浅溝素子分離構造に直接重なる導電層の部分の上面より高く延びる導電層の部分を除去することによって、導電層を平坦化するステップと、
平坦化された導電層を通じて、浅溝素子分離構造にイオンを注入するステップと、
その後、第1の導電層を除去し、その後、浅溝素子分離構造のうちの注入イオン濃度がしきい値を超える部分はエッチングするが浅溝素子分離構造のうちの注入イオン濃度がしきい値を下回る部分は除去しないステップと、
を含む方法。 - 請求項7記載の方法において、
浅溝素子分離構造に直接重なる導電層の部分の上面より高く延びる導電層の部分を除去するステップは、化学的機械的研磨によって行われる方法。 - 請求項8記載の方法において、
化学的機械的研磨は、基板と、浅溝素子分離構造に直接重なる導電層の部分の上面より高く延びる導電層の部分は腐食するが浅溝素子分離構造に直接重なる導電層の部分の上面は著しく腐食しないパッドと間の圧力によって行われる方法。
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US11/254,142 US7541240B2 (en) | 2005-10-18 | 2005-10-18 | Integration process flow for flash devices with low gap fill aspect ratio |
US11/254,142 | 2005-10-18 | ||
PCT/US2006/039931 WO2007047390A2 (en) | 2005-10-18 | 2006-10-10 | Integration process flow for flash devices |
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KR (1) | KR101029696B1 (ja) |
CN (1) | CN101288164B (ja) |
AT (1) | ATE526682T1 (ja) |
TW (1) | TWI384588B (ja) |
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WO2007047390A3 (en) | 2007-06-14 |
ATE526682T1 (de) | 2011-10-15 |
KR101029696B1 (ko) | 2011-04-18 |
TW200731473A (en) | 2007-08-16 |
EP2320455B1 (en) | 2012-07-18 |
EP2320455A1 (en) | 2011-05-11 |
EP1938371B1 (en) | 2011-09-28 |
EP1938371A2 (en) | 2008-07-02 |
WO2007047390A2 (en) | 2007-04-26 |
JP2009512228A (ja) | 2009-03-19 |
US7541240B2 (en) | 2009-06-02 |
CN101288164A (zh) | 2008-10-15 |
TWI384588B (zh) | 2013-02-01 |
KR20080075086A (ko) | 2008-08-14 |
US20070087504A1 (en) | 2007-04-19 |
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