JP4926869B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP4926869B2
JP4926869B2 JP2007194100A JP2007194100A JP4926869B2 JP 4926869 B2 JP4926869 B2 JP 4926869B2 JP 2007194100 A JP2007194100 A JP 2007194100A JP 2007194100 A JP2007194100 A JP 2007194100A JP 4926869 B2 JP4926869 B2 JP 4926869B2
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JP
Japan
Prior art keywords
wiring board
cavity
semiconductor device
manufacturing
mold
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2007194100A
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English (en)
Japanese (ja)
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JP2009032842A (ja
JP2009032842A5 (https=
Inventor
文司 倉冨
福美 清水
洋一 河田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2007194100A priority Critical patent/JP4926869B2/ja
Publication of JP2009032842A publication Critical patent/JP2009032842A/ja
Publication of JP2009032842A5 publication Critical patent/JP2009032842A5/ja
Application granted granted Critical
Publication of JP4926869B2 publication Critical patent/JP4926869B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
JP2007194100A 2007-07-26 2007-07-26 半導体装置の製造方法 Expired - Fee Related JP4926869B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007194100A JP4926869B2 (ja) 2007-07-26 2007-07-26 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007194100A JP4926869B2 (ja) 2007-07-26 2007-07-26 半導体装置の製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2011168249A Division JP5419230B2 (ja) 2011-08-01 2011-08-01 半導体装置およびその製造方法

Publications (3)

Publication Number Publication Date
JP2009032842A JP2009032842A (ja) 2009-02-12
JP2009032842A5 JP2009032842A5 (https=) 2010-08-26
JP4926869B2 true JP4926869B2 (ja) 2012-05-09

Family

ID=40403060

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007194100A Expired - Fee Related JP4926869B2 (ja) 2007-07-26 2007-07-26 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JP4926869B2 (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011035142A (ja) * 2009-07-31 2011-02-17 Sanyo Electric Co Ltd 回路装置の製造方法
JP2013191690A (ja) 2012-03-13 2013-09-26 Shin Etsu Chem Co Ltd 半導体装置及びその製造方法
JP5969883B2 (ja) 2012-10-03 2016-08-17 信越化学工業株式会社 半導体装置の製造方法
JP2014103176A (ja) 2012-11-16 2014-06-05 Shin Etsu Chem Co Ltd 支持基材付封止材、封止後半導体素子搭載基板、封止後半導体素子形成ウエハ、半導体装置、及び半導体装置の製造方法
JP6115505B2 (ja) 2013-06-21 2017-04-19 株式会社デンソー 電子装置
JP6125371B2 (ja) 2013-08-15 2017-05-10 信越化学工業株式会社 半導体装置の製造方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11198185A (ja) * 1998-01-19 1999-07-27 Nec Corp 射出圧等圧機構を有する樹脂封止金型
JP4115228B2 (ja) * 2002-09-27 2008-07-09 三洋電機株式会社 回路装置の製造方法
JP2005085832A (ja) * 2003-09-05 2005-03-31 Apic Yamada Corp 樹脂モールド装置
JP2007109831A (ja) * 2005-10-13 2007-04-26 Towa Corp 電子部品の樹脂封止成形方法

Also Published As

Publication number Publication date
JP2009032842A (ja) 2009-02-12

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