JP4771750B2 - 線幅の狭い半導体素子の製造方法 - Google Patents
線幅の狭い半導体素子の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 28
- 238000004519 manufacturing process Methods 0.000 title claims description 21
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 66
- 238000005530 etching Methods 0.000 claims description 66
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 66
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 51
- 229910052710 silicon Inorganic materials 0.000 claims description 51
- 239000010703 silicon Substances 0.000 claims description 51
- 230000002093 peripheral effect Effects 0.000 claims description 46
- 229920002120 photoresistant polymer Polymers 0.000 claims description 33
- 238000000034 method Methods 0.000 claims description 30
- 238000007740 vapor deposition Methods 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 9
- 229920000642 polymer Polymers 0.000 claims description 5
- 239000007789 gas Substances 0.000 description 23
- 230000015572 biosynthetic process Effects 0.000 description 7
- 239000000203 mixture Substances 0.000 description 7
- 230000007423 decrease Effects 0.000 description 6
- 230000007261 regionalization Effects 0.000 description 4
- 101001027622 Homo sapiens Protein adenylyltransferase FICD Proteins 0.000 description 2
- 102100037689 Protein adenylyltransferase FICD Human genes 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
- 230000003667 anti-reflective effect Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Description
201A シリコン窒化膜
202A シリコン酸窒化膜
201B パターニングされたシリコン窒化膜
202B パターニングされたシリコン酸窒化膜
203 フォトレジストパターン
300 基板
301A ゲート導電膜
302A シリコン窒化膜
303A シリコン酸窒化膜
301B パターニングされたゲート導電膜
302B パターニングされたシリコン窒化膜
303B パターニングされたシリコン酸窒化膜
304 フォトレジストパターン
W1 セル領域におけるDICD
W1A セル領域におけるFICD
W2 周辺領域におけるDICD
W2A 周辺領域におけるFICD
A セル領域
B 周辺領域
Claims (8)
- セル領域及び周辺領域が画定された基板上に蒸着によってシリコン窒化膜を形成する第1ステップ、
前記シリコン窒化膜上に蒸着によって反射防止膜としてシリコン酸窒化膜を形成する第2ステップ、
前記シリコン酸窒化膜上に、前記セル領域では、最終パターンの線幅より、後続のエッチングによって狭まる線幅の大きさの分だけ広い幅を有する線状のフォトレジストパターンを形成し、前記周辺領域では、周辺領域でのパターンの崩れの発生を抑える最小の線幅を有する線状のフォトレジストパターンを形成する第3ステップ、
ポリマーの発生を抑制しながら、各セル領域及び周辺領域に幅が異なるように形成された前記フォトレジストパターンをエッチングマスクとして前記シリコン酸窒化膜と前記シリコン窒化膜とを順次にガスを用いてエッチングする処理を、エッチング後に残留する前記シリコン酸窒化膜と前記シリコン窒化膜との線幅が前記フォトレジストパターンの線幅に比べて狭くなり、前記セル領域では前記シリコン酸窒化膜および前記シリコン窒化膜の線幅が最終パターンの線幅になるまで行う第4ステップ、及び
前記第4ステップの後に残留する前記シリコン窒化膜を過度エッチングする第5ステップを含み、
前記第4ステップにおいて、
前記シリコン酸窒化膜をエッチングする際に、CHF 3 とCF 4 との混合比が、CF 4 を1としてCHF 3 が1.1〜1.6である混合ガスを使用し、前記シリコン窒化膜をエッチングする際に、CHF 3 とCF 4 との混合比が、CHF 3 を1としてCF 4 が1.1〜2である混合ガスを使用することを特徴とする半導体素子の製造方法。 - 残留する前記シリコン窒化膜を過度エッチングする前記第5ステップにおいて、エッチングガスとしてCHF3とCF4との混合ガスを用いることを特徴とする請求項1に記載の半導体素子の製造方法。
- 前記シリコン酸窒化膜と前記シリコン窒化膜とを順次にガスを用いてエッチングする前記第4ステップにおいて、ウェハチャックの温度を50℃以上に維持することを特徴とする請求項2に記載の半導体素子の製造方法。
- 残留する前記シリコン窒化膜を過度エッチングする前記第5ステップにおいて、CHF3とCF4との混合比が、CF4を1としてCHF3が1.5〜3である混合ガスを使用することを特徴とする請求項2に記載の半導体素子の製造方法。
- セル領域及び周辺領域が画定された基板上に蒸着によって導電膜を形成する第1ステップ、
前記導電膜上に蒸着によって絶縁性ハードマスクとしてシリコン窒化膜を形成する第2ステップ、
前記シリコン窒化膜上に蒸着によって反射防止膜としてシリコン酸窒化膜を形成する第3ステップ、
前記シリコン酸窒化膜上に、前記セル領域では、最終パターンの線幅より、後続のエッチングによって狭まる線幅の大きさの分だけ広い幅を有する線状のフォトレジストパターンを形成し、前記周辺領域では、周辺領域でのパターンの崩れの発生を抑える最小の線幅を有する線状のフォトレジストパターンを形成する第4ステップ、
ポリマーの発生を抑制しながら、各セル領域及び周辺領域に幅が異なるように形成された前記フォトレジストパターンをエッチングマスクとして前記シリコン酸窒化膜と前記シリコン窒化膜とを順次にガスを用いてエッチングする処理を、エッチング後に残留する前記シリコン酸窒化膜と前記シリコン窒化膜との線幅が前記フォトレジストパターンの線幅に比べて狭くなり、前記セル領域では前記シリコン酸窒化膜および前記シリコン窒化膜の線幅が最終パターンの線幅になるまで行う第5ステップ、
前記第5ステップの後に残留する前記シリコン窒化膜を過度エッチングする第6ステップ、
前記フォトレジストパターンを除去する第7ステップ、
前記第7ステップの後に残留する前記シリコン酸窒化膜と前記シリコン窒化膜とをエッチングマスクとして前記導電膜をエッチングする第8ステップ、及び
前記第8ステップの後に残留する前記シリコン酸窒化膜を除去する第9ステップを含み、
前記第5ステップにおいて、
前記シリコン酸窒化膜をエッチングする際に、CHF 3 とCF 4 との混合比が、CF 4 を1としてCHF 3 が1.1〜1.6である混合ガスを使用し、前記シリコン窒化膜をエッチングする際に、CHF 3 とCF 4 との混合比が、CHF 3 を1としてCF 4 が1.1〜2である混合ガスを使用することを特徴とする半導体素子の製造方法。 - 残留する前記シリコン窒化膜を過度エッチングする前記第6ステップにおいて、エッチングガスとしてCHF3とCF4との混合ガスを用いることを特徴とする請求項5に記載の半導体素子の製造方法。
- 前記シリコン酸窒化膜と前記シリコン窒化膜とを順次にガスを用いてエッチングする前記第5ステップにおいて、ウェハチャックの温度を50℃以上に維持することを特徴とする請求項6に記載の半導体素子の製造方法。
- 残留する前記シリコン窒化膜を過度エッチングする前記第6ステップにおいて、CHF3とCF4との混合比が、CF4を1としてCHF3が1.5〜3である混合ガスを使用することを特徴とする請求項6に記載の半導体素子の製造方法。
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KR1020040048365A KR100706780B1 (ko) | 2004-06-25 | 2004-06-25 | 주변영역의 선폭을 줄일 수 있는 반도체 소자 제조 방법 |
KR10-2004-0048365 | 2004-06-25 |
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US (3) | US7179749B2 (ja) |
JP (1) | JP4771750B2 (ja) |
KR (1) | KR100706780B1 (ja) |
CN (1) | CN100345282C (ja) |
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JP2006013485A (ja) | 2006-01-12 |
US7563721B2 (en) | 2009-07-21 |
US7179749B2 (en) | 2007-02-20 |
US20050287809A1 (en) | 2005-12-29 |
CN100345282C (zh) | 2007-10-24 |
TWI264065B (en) | 2006-10-11 |
US20090253263A1 (en) | 2009-10-08 |
KR20050122737A (ko) | 2005-12-29 |
TW200605200A (en) | 2006-02-01 |
US20070184664A1 (en) | 2007-08-09 |
KR100706780B1 (ko) | 2007-04-11 |
CN1722409A (zh) | 2006-01-18 |
US7803710B2 (en) | 2010-09-28 |
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