TWI264065B - Method for fabricating semiconductor device capable of decreasing critical dimension in peripheral region - Google Patents

Method for fabricating semiconductor device capable of decreasing critical dimension in peripheral region

Info

Publication number
TWI264065B
TWI264065B TW094118829A TW94118829A TWI264065B TW I264065 B TWI264065 B TW I264065B TW 094118829 A TW094118829 A TW 094118829A TW 94118829 A TW94118829 A TW 94118829A TW I264065 B TWI264065 B TW I264065B
Authority
TW
Taiwan
Prior art keywords
peripheral region
silicon nitride
nitride layer
photoresist pattern
semiconductor device
Prior art date
Application number
TW094118829A
Other languages
English (en)
Other versions
TW200605200A (en
Inventor
Kyung-Won Lee
Ki-Won Nam
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of TW200605200A publication Critical patent/TW200605200A/zh
Application granted granted Critical
Publication of TWI264065B publication Critical patent/TWI264065B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31144Etching the insulating layers by chemical or physical means using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338Process specially adapted to improve the resolution of the mask
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/01Manufacture or treatment
    • H10B12/09Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
TW094118829A 2004-06-25 2005-06-07 Method for fabricating semiconductor device capable of decreasing critical dimension in peripheral region TWI264065B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020040048365A KR100706780B1 (ko) 2004-06-25 2004-06-25 주변영역의 선폭을 줄일 수 있는 반도체 소자 제조 방법

Publications (2)

Publication Number Publication Date
TW200605200A TW200605200A (en) 2006-02-01
TWI264065B true TWI264065B (en) 2006-10-11

Family

ID=35506461

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094118829A TWI264065B (en) 2004-06-25 2005-06-07 Method for fabricating semiconductor device capable of decreasing critical dimension in peripheral region

Country Status (5)

Country Link
US (3) US7179749B2 (zh)
JP (1) JP4771750B2 (zh)
KR (1) KR100706780B1 (zh)
CN (1) CN100345282C (zh)
TW (1) TWI264065B (zh)

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KR100706780B1 (ko) 2004-06-25 2007-04-11 주식회사 하이닉스반도체 주변영역의 선폭을 줄일 수 있는 반도체 소자 제조 방법
KR100571629B1 (ko) 2004-08-31 2006-04-17 주식회사 하이닉스반도체 반도체 소자 제조 방법
KR100788587B1 (ko) * 2006-07-05 2007-12-26 주식회사 하이닉스반도체 플래쉬 메모리 소자의 제조방법
KR100954107B1 (ko) 2006-12-27 2010-04-23 주식회사 하이닉스반도체 반도체 소자의 제조방법
KR100780606B1 (ko) 2006-12-27 2007-11-30 주식회사 하이닉스반도체 반도체 소자의 제조방법
KR100780652B1 (ko) 2006-12-27 2007-11-30 주식회사 하이닉스반도체 반도체 소자 제조방법
KR100875655B1 (ko) 2007-01-04 2008-12-26 주식회사 하이닉스반도체 반도체 소자의 제조방법
KR100843899B1 (ko) * 2007-03-19 2008-07-03 주식회사 하이닉스반도체 반도체 소자의 제조방법
JP2009152243A (ja) * 2007-12-18 2009-07-09 Toshiba Corp 半導体装置の製造方法
CN101740328B (zh) * 2008-11-13 2012-03-07 中芯国际集成电路制造(上海)有限公司 刻蚀方法
KR20100079081A (ko) * 2008-12-30 2010-07-08 주식회사 동부하이텍 엠아이엠 커패시터 및 그의 제조 방법
US7989355B2 (en) * 2009-02-12 2011-08-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of pitch halving
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US8293656B2 (en) 2009-05-22 2012-10-23 Applied Materials, Inc. Selective self-aligned double patterning of regions in an integrated circuit device
CN101777493A (zh) * 2010-01-28 2010-07-14 上海宏力半导体制造有限公司 硬掩膜层刻蚀方法
CN102931089B (zh) * 2011-08-10 2016-08-03 无锡华润上华半导体有限公司 Ldmos器件及其制造方法
US8872339B2 (en) * 2012-02-10 2014-10-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductors structure with elements having different widths and methods of making the same
TWI571699B (zh) * 2014-12-26 2017-02-21 旺宏電子股份有限公司 佈局圖案以及包含該佈局圖案的光罩
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Also Published As

Publication number Publication date
JP4771750B2 (ja) 2011-09-14
JP2006013485A (ja) 2006-01-12
US7563721B2 (en) 2009-07-21
US7179749B2 (en) 2007-02-20
US20050287809A1 (en) 2005-12-29
CN100345282C (zh) 2007-10-24
US20090253263A1 (en) 2009-10-08
KR20050122737A (ko) 2005-12-29
TW200605200A (en) 2006-02-01
US20070184664A1 (en) 2007-08-09
KR100706780B1 (ko) 2007-04-11
CN1722409A (zh) 2006-01-18
US7803710B2 (en) 2010-09-28

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