JP4743348B2 - 薄膜トランジスタアレイおよび薄膜トランジスタアレイを用いた画像表示装置 - Google Patents
薄膜トランジスタアレイおよび薄膜トランジスタアレイを用いた画像表示装置 Download PDFInfo
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- JP4743348B2 JP4743348B2 JP2010539967A JP2010539967A JP4743348B2 JP 4743348 B2 JP4743348 B2 JP 4743348B2 JP 2010539967 A JP2010539967 A JP 2010539967A JP 2010539967 A JP2010539967 A JP 2010539967A JP 4743348 B2 JP4743348 B2 JP 4743348B2
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- film transistor
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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- G—PHYSICS
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
- G02F2201/40—Arrangements for improving the aperture ratio
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Description
前記薄膜トランジスタは、前記ソース配線の領域内に形成され、前記ソース配線及び前記半導体層を覆うようにストライプ状絶縁膜を有していることを特徴とする薄膜トランジスタアレイとしたものである。
図1は、本発明の実施の形態に係る薄膜トランジスタアレイを示す概略模式図であり、図2(a)は、図1に示す薄膜トランジスタアレイの1画素分(S1領域)を示す概略模式図であり、図2(b)は、図2(a)に示すa−b間の概略断面模式図である。図1では、左側の列の薄膜トランジスタの半導体層12については、境界線のみを実線で示している。図2以降においても同様に特に断りのない場合には、半導体層は境界線のみあるいは一部のみをハッチングして示す。図1及び2に示すように、本発明の実施の形態に係る薄膜トランジスタアレイは、基板10上に形成されたゲート電極21と、ゲート電極21上に形成されたゲート絶縁層11と、ゲート絶縁層11上に形成されたソース電極27及び画素電極25に接続されたドレイン電極26と、ソース電極27及びドレイン電極26の間に形成された半導体層12とを有する薄膜トランジスタをマトリクス状に配置されている。各薄膜トランジスタはゲート電極21をゲート配線22に、ソース電極27をソース配線28にそれぞれ接続した構成であり、ドレイン電極26がソース配線領域28A内に形成されている。
図10は、本発明の実施の形態に係る薄膜トランジスタアレイを示す概略模式図であり、図11(a)は、図10に示す薄膜トランジスタアレイの1画素分(S1領域)示す概略模式図である。図11(b)は、図11(a)において、ゲート配線22と、キャパシタ電極23、キャパシタ配線24と、薄膜トランジスタ領域S2及び画素電極領域S3を示す概略模式図である。図11(c)は、図11(a)に示すe−f間の概略断面模式図である。図10及び11に示すように、本発明の実施の形態に係る薄膜トランジスタアレイは、基板10上に形成されたゲート電極21と、ゲート電極21上に形成されたゲート絶縁層11と、ゲート絶縁層11上に形成されたソース電極27及び画素電極25に接続されたドレイン電極26と、ソース電極27及びドレイン電極26の間に形成された半導体層12とを有する薄膜トランジスタをマトリクス状に配置されている。ゲート配線22はゲート配線21を兼ね、ソース電極27をソース配線28にそれぞれ接続した構成である。ドレイン電極26はゲート配線22の領域内に形成されている。
4を形成した。
本比較例1では、図26及び27に示す、ボトムゲート・ボトムコンタクト型薄膜トランジスタアレイの作製方法を示す。図26は、本実施例の形態に係る薄膜トランジスタアレイを示す概略模式図であり、図27(a)は、図26に示す薄膜トランジスタアレイの1画素分の製造工程途中を示す概略模式図であり、図27(b)は、図26に示す薄膜トランジスタアレイの1画素分を示す概略模式図であり、図27(c)は、図27(b)に示すs−t間の概略断面模式図である。比較例1の薄膜トランジスタアレイは1画素が500μm角、配線幅が25μm、チャネル長が5μm、チャネル幅が500μmであり、ソース電極27・ドレイン電極26はソース配線28の外に形成する。なお、図の縮尺は実際のものとは異なる。
Claims (10)
- 基板上に形成されたゲート電極と、前記ゲート電極上に形成されたゲート絶縁層と、前記ゲート絶縁層上に形成されたソース電極及び画素電極に接続されたドレイン電極と、前記ソース電極及び前記ドレイン電極の間に形成された半導体層とを有する薄膜トランジスタをマトリクス状に配置し、前記ゲート電極をゲート配線に、前記ソース電極をソース配線にそれぞれ接続した薄膜トランジスタアレイであって、
前記薄膜トランジスタは、前記ソース配線の領域内に形成され、前記ソース配線及び前記半導体層を覆うようにストライプ状絶縁膜を有していることを特徴とする薄膜トランジスタアレイ。 - 前記ソース配線はその一部に切り欠き部を有し、前記切り欠き部に前記ドレイン電極が形成され、ソース配線がソース電極を兼ねていることを特徴とする請求項1に記載の薄膜トランジスタアレイ。
- 前記ドレイン電極が、ソース配線の切り欠きに入り込むくし型に形成されていることを特徴とする請求項2に記載の薄膜トランジスタアレイ。
- 前記ドレイン電極が前記ソース配線領域のほぼ中心線に沿った直線状であり、前記ソース配線が前記ソース電極を兼ねて形成され、前記ソース電極が前記ドレイン電極をほぼ囲む形状であることを特徴とする請求項2に記載の薄膜トランジスタアレイ。
- 前記ソース配線の切り欠きが長方形であり、該ソース配線領域のほぼ中央線を間隙として、前記ドレイン電極が前記ソース配線の切り欠きを除いた部分と向かい合う形状であることを特徴とする請求項2に記載の薄膜トランジスタアレイ。
- 前記半導体層が前記ソース配線領域のほぼ中心線に沿った直線状であることを特徴とする請求項1乃至5のいずれかに記載の薄膜トランジスタアレイ。
- 前記半導体層が前記ソース配線と平行であり、かつ複数の画素に連続したストライプ形状であることを特徴とする請求項6に記載の薄膜トランジスタアレイ。
- 前記半導体層が有機半導体若しくは酸化物半導体であることを特徴とする請求項1乃至7のいずれかに記載の薄膜トランジスタアレイ。
- 前記ゲート電極と同じ層にキャパシタ電極を有することを特徴とする請求項1乃至8のいずれかに記載の薄膜トランジスタアレイ。
- 請求項1乃至9のいずれかに記載の薄膜トランジスタアレイを用いたことを特徴とする画像表示装置。
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PCT/JP2010/054439 WO2010107027A1 (ja) | 2009-03-17 | 2010-03-16 | 薄膜トランジスタアレイおよび薄膜トランジスタアレイを用いた画像表示装置 |
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