JP4712940B2 - 電子部材の製造方法 - Google Patents

電子部材の製造方法 Download PDF

Info

Publication number
JP4712940B2
JP4712940B2 JP2000208458A JP2000208458A JP4712940B2 JP 4712940 B2 JP4712940 B2 JP 4712940B2 JP 2000208458 A JP2000208458 A JP 2000208458A JP 2000208458 A JP2000208458 A JP 2000208458A JP 4712940 B2 JP4712940 B2 JP 4712940B2
Authority
JP
Japan
Prior art keywords
layer
electroless plating
wiring
resist
plating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2000208458A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001085567A (ja
JP2001085567A5 (enExample
Inventor
悟 倉持
真史 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dai Nippon Printing Co Ltd
Original Assignee
Dai Nippon Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dai Nippon Printing Co Ltd filed Critical Dai Nippon Printing Co Ltd
Priority to JP2000208458A priority Critical patent/JP4712940B2/ja
Publication of JP2001085567A publication Critical patent/JP2001085567A/ja
Publication of JP2001085567A5 publication Critical patent/JP2001085567A5/ja
Application granted granted Critical
Publication of JP4712940B2 publication Critical patent/JP4712940B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Chemically Coating (AREA)
  • Electroplating Methods And Accessories (AREA)
JP2000208458A 1999-07-12 2000-07-10 電子部材の製造方法 Expired - Fee Related JP4712940B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000208458A JP4712940B2 (ja) 1999-07-12 2000-07-10 電子部材の製造方法

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP1999198203 1999-07-12
JP11-198203 1999-07-12
JP19820399 1999-07-12
JP2000208458A JP4712940B2 (ja) 1999-07-12 2000-07-10 電子部材の製造方法

Publications (3)

Publication Number Publication Date
JP2001085567A JP2001085567A (ja) 2001-03-30
JP2001085567A5 JP2001085567A5 (enExample) 2007-06-14
JP4712940B2 true JP4712940B2 (ja) 2011-06-29

Family

ID=26510838

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000208458A Expired - Fee Related JP4712940B2 (ja) 1999-07-12 2000-07-10 電子部材の製造方法

Country Status (1)

Country Link
JP (1) JP4712940B2 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3860000B2 (ja) 2001-09-07 2006-12-20 Necエレクトロニクス株式会社 半導体装置およびその製造方法
TWI312166B (en) * 2001-09-28 2009-07-11 Toppan Printing Co Ltd Multi-layer circuit board, integrated circuit package, and manufacturing method for multi-layer circuit board
KR100582425B1 (ko) 2006-01-16 2006-05-23 (주)플렉스컴 회로기판의 비어홀 필링방법

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4060905B2 (ja) * 1997-04-02 2008-03-12 大日本印刷株式会社 半導体装置用回路部材とそれを用いた半導体装置、及びそれらの製造方法
JP3688397B2 (ja) * 1996-06-19 2005-08-24 日本アビオニクス株式会社 メタルコアプリント配線板およびその製造方法
JP3589794B2 (ja) * 1996-06-25 2004-11-17 富士通株式会社 外部接続用電極の製造方法及び外部接続用電極及び 半導体装置
JP3777687B2 (ja) * 1996-12-12 2006-05-24 凸版印刷株式会社 チップキャリア
JPH10296635A (ja) * 1997-04-23 1998-11-10 Toyota Motor Corp ウエットブラスト装置
JP3126331B2 (ja) * 1997-10-29 2001-01-22 イビデン株式会社 パッケージ基板
JP3444769B2 (ja) * 1997-11-25 2003-09-08 東洋アルミニウム株式会社 集電体用アルミニウム箔とその製造方法、集電体、二次電池および電気二重層コンデンサ
JP3250519B2 (ja) * 1998-05-08 2002-01-28 関西日本電気株式会社 配線基板の製造方法
JP2000091719A (ja) * 1998-07-16 2000-03-31 Dainippon Printing Co Ltd 絶縁被膜付き部材とそれを用いた配線基板、及び絶縁被膜付き部材の製造方法と配線基板の製造方法

Also Published As

Publication number Publication date
JP2001085567A (ja) 2001-03-30

Similar Documents

Publication Publication Date Title
KR101014576B1 (ko) 반도체 탑재용 기판
CN1327499C (zh) 制造半导体组件的方法
US7303978B2 (en) Board for mounting BGA semiconductor chip thereon, semiconductor device, and methods of fabricating such board and semiconductor device
TWI246753B (en) Package substrate for electrolytic leadless plating and manufacturing method thereof
TW200301554A (en) Method of producing multilayered circuit board for semiconductor device
JP2010157718A (ja) プリント配線板及びプリント配線板の製造方法
JP2006216712A (ja) 多層プリント配線板
CN100524724C (zh) 线焊焊盘和球形焊盘之间厚度不同的半导体封装基片的制造方法
CN1225950C (zh) 电路板
KR20050033821A (ko) 반도체장치 및 그 제조 방법
JP3197540B2 (ja) 基板素片、及びフレキシブル基板
JP4712940B2 (ja) 電子部材の製造方法
JP3981227B2 (ja) 多層配線基板とその製造方法
JP2009277987A (ja) 電子部品実装用フィルムキャリアテープ、その製造方法、および、半導体装置
JP2006216711A (ja) 多層プリント配線板
JP3598525B2 (ja) 電子部品搭載用多層基板の製造方法
JP4353873B2 (ja) プリント配線板
JP2013122962A (ja) 配線基板
JP2005150417A (ja) 半導体装置用基板及びその製造方法並びに半導体装置
JP2010153438A (ja) 部品内蔵基板の製造方法
JP2002190549A (ja) 多層配線板および多層配線板の製造方法
JP4826103B2 (ja) 半導体装置用基板、および半導体素子用bgaパッケージ
KR101154352B1 (ko) 임베디드 인쇄회로기판용 부재 및 그 제조 방법 및 임베디드 인쇄회로기판용 부재를 이용한 임베디드 인쇄회로기판 제조 방법
KR101231343B1 (ko) 인쇄회로기판 및 그의 제조 방법
JP3759755B2 (ja) 恒久的接続のために電気回路の上に隆起した金属接点を作成する方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070426

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070427

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20070820

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100311

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100427

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20101109

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20101224

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20110301

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20110324

LAPS Cancellation because of no payment of annual fees