JP4675844B2 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- JP4675844B2 JP4675844B2 JP2006187597A JP2006187597A JP4675844B2 JP 4675844 B2 JP4675844 B2 JP 4675844B2 JP 2006187597 A JP2006187597 A JP 2006187597A JP 2006187597 A JP2006187597 A JP 2006187597A JP 4675844 B2 JP4675844 B2 JP 4675844B2
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- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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Description
Claims (16)
- 半導体基板上に配されたnチャネルトランジスタと、
半導体基板上に配されたpチャネルトランジスタと、
上記nチャネルトランジスタと上記pチャネルトランジスタとに接触する圧電層と、
上記圧電層に電位を与える導電部とを備え、
上記nチャネルトランジスタに引っ張り応力がかかり、上記pチャネルトランジスタに圧縮応力がかかるように、上記導電部から、上記圧電層のnチャネルトランジスタに接触する部分およびpチャネルトランジスタに接触する部分にそれぞれ異なる所定の電位が与えられることを特徴とする半導体装置。 - 上記圧電層は、ZnO、Bi12GeO20、BatiO3、PMNおよびそれらの化合物からなる群から選択される物質を含んでいることを特徴とする請求項1に記載の半導体装置。
- 上記圧電層は、上記nチャネルトランジスタおよび上記pチャネルトランジスタを覆っていることを特徴とする請求項1に記載の半導体装置。
- 上記導電部は、上記nチャネルトランジスタおよび上記pチャネルトランジスタを覆う導電層であることを特徴とする請求項3に記載の半導体装置。
- 上記nチャネルトランジスタを覆う、上記圧電層の部分は、上記pチャネルトランジスタを覆う、上記圧電層の部分から分離されていることを特徴とする請求項4に記載の半導体装置。
- 上記圧電層は、分離溝内に配されていることを特徴とする請求項1に記載の半導体装置。
- 上記導電部は、上記分離溝内に配されていることを特徴とする請求項6に記載の半導体装置。
- 上記半導体基板は、絶縁層を覆う半導体層を含み、
上記絶縁層は、基板を覆っていることを特徴とする請求項1に記載の半導体装置。 - 上記圧電層は、上記半導体層の下に配されていることを特徴とする請求項8に記載の半導体装置。
- 上記絶縁層は、上記圧電層であることを特徴とする請求項9に記載の半導体装置。
- 上記圧電層は、上記半導体層と上記絶縁層との間に配されていることを特徴とする請求項9に記載の半導体装置。
- 半導体基板の表面にnチャネルトランジスタおよびpチャネルトランジスタを形成する工程と、
上記nチャネルトランジスタと上記pチャネルトランジスタとに接触する圧電層を形成する工程と、
上記圧電層に電位を与える導電部を形成する工程と、
上記圧電層の少なくとも一部を電圧接点に電気的に接続する工程とを含み、
上記導電部は、上記nチャネルトランジスタに引っ張り応力がかかり、上記pチャネルトランジスタに圧縮応力がかかるように、上記圧電層のnチャネルトランジスタに接触する部分およびpチャネルトランジスタに接触する部分にそれぞれ異なる所定の電位を与えることを特徴とする半導体装置の製造方法。 - 上記電圧接点は、上記トランジスタが起動した時に上記圧電層によって当該トランジスタに応力がかかるようにする信号を伝達することを特徴とする請求項12に記載の半導体装置の製造方法。
- 上記トランジスタに接触する圧電層を形成する工程は、上記トランジスタ上に圧電層を形成する工程を含むことを特徴とする請求項12に記載の半導体装置の製造方法。
- 上記トランジスタに接触する圧電層を形成する工程は、上記トランジスタに隣接する分離溝の内部に圧電層を形成する工程を含むことを特徴とする請求項12に記載の半導体装置の製造方法。
- 上記トランジスタに接触する圧電層を形成する工程は、上記圧電層の上に上記トランジスタを形成する工程を含むことを特徴とする請求項12に記載の半導体装置の製造方法。
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US11/176,727 US7586158B2 (en) | 2005-07-07 | 2005-07-07 | Piezoelectric stress liner for bulk and SOI |
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US20070018328A1 (en) | 2007-01-25 |
JP2007019515A (ja) | 2007-01-25 |
DE102006062916B3 (de) | 2014-10-16 |
DE102006062917B4 (de) | 2017-03-23 |
DE102006029235B4 (de) | 2013-10-17 |
US7586158B2 (en) | 2009-09-08 |
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