JP4556757B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP4556757B2 JP4556757B2 JP2005131009A JP2005131009A JP4556757B2 JP 4556757 B2 JP4556757 B2 JP 4556757B2 JP 2005131009 A JP2005131009 A JP 2005131009A JP 2005131009 A JP2005131009 A JP 2005131009A JP 4556757 B2 JP4556757 B2 JP 4556757B2
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- 239000004065 semiconductor Substances 0.000 title claims description 24
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000002184 metal Substances 0.000 claims description 40
- 238000000034 method Methods 0.000 claims description 19
- 229920002120 photoresistant polymer Polymers 0.000 claims description 18
- 238000010438 heat treatment Methods 0.000 claims description 8
- 229920003986 novolac Polymers 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- 125000000664 diazo group Chemical group [N-]=[N+]=[*] 0.000 claims description 2
- 239000002904 solvent Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 79
- 239000002923 metal particle Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 4
- 230000018109 developmental process Effects 0.000 description 4
- 239000003960 organic solvent Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 229910001111 Fine metal Inorganic materials 0.000 description 2
- MVPPADPHJFYWMZ-UHFFFAOYSA-N chlorobenzene Chemical compound ClC1=CC=CC=C1 MVPPADPHJFYWMZ-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 230000007261 regionalization Effects 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 238000001771 vacuum deposition Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 150000001412 amines Chemical class 0.000 description 1
- 239000003054 catalyst Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
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Classifications
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/004—Photosensitive materials
- G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
- G03F7/095—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers having more than one photosensitive layer
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
- C23F1/00—Etching metallic material by chemical means
- C23F1/02—Local etching
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/20—Exposure; Apparatus therefor
- G03F7/2022—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32051—Deposition of metallic or metal-silicide layers
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
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- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Mechanical Engineering (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Structural Engineering (AREA)
- Organic Chemistry (AREA)
- Metallurgy (AREA)
- Materials Engineering (AREA)
- General Chemical & Material Sciences (AREA)
- Architecture (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Electrodes Of Semiconductors (AREA)
- Weting (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Description
前記フォトレジスト膜を現像することにより、前記表面レジスト層が逆テーパ形状であり、前記下層レジスト層が前記表面レジスト層に対してアンダーカット形状であるレジストパターンに加工する工程と、
前記レジストパターン上に電極、配線材料となる金属膜を形成する工程と、
前記レジストパターンを溶剤で溶解させるとともに前記レジストパターン上の前記金属膜を除去する工程と、を含むことを特徴とする半導体装置の製造方法を提供する。
以下に、本実施の形態におけるレジストパターンの製造方法を図2(a)から(e)を参照しながら説明する。
(1)図1に示したように、確実にレジスト側壁部で金属膜の段切れを生じさせることにより、リフトオフ処理時間は大幅に短縮され、かつ金属パターン20pの外周部にはバリは全く発生しない。
(2)金属パターンの寸法精度については半導体素子を製造する上で求められる精度に合せ、レジスト断面形状を制御することにより必要な寸法精度が得られる。
11 半導体ウエハ
13 下層のレジスト層
15 表面レジスト層
20 金属膜
20p 金属パターン
20o 金属膜
20s 側壁付着層
41 半導体ウエハ
43 レジスト層
45 金属膜
45a,45b,45c バリ
45s 側壁付着層
51 レジスト層
Claims (2)
- 基板上或いはその上に形成された被膜上に、ジアゾ・ノボラック型のポジ型フォトレジストにより1.5〜2.5μmの膜厚の下層のレジスト層を形成し、全面露光量90mj/cm 2 ・secから300mj/cm 2 ・secの範囲で全面露光する工程と、
前記全面露光された前記下層のレジスト層上に、露光後熱処理のみによりネガ型に反転するポジ型フォトレジストにより2.5〜3.5μmの膜厚の表面レジスト層を形成する工程と、
前記下層のレジスト層と前記表面レジスト層からなるフォトレジスト膜にパターン露光及び熱処理を行って前記表面レジスト層のパターン露光部をネガ型に反転させる工程と、
前記フォトレジスト膜に全面露光を行う工程と、
前記フォトレジスト膜を現像することにより、前記表面レジスト層が逆テーパ形状であり、前記下層レジスト層が前記表面レジスト層に対してアンダーカット形状であるレジストパターンに加工する工程と、
前記レジストパターン上に電極、配線材料となる金属膜を形成する工程と、
前記レジストパターンを溶剤で溶解させるとともに前記レジストパターン上の前記金属膜を除去する工程と、
を含むことを特徴とする半導体装置の製造方法。 - 前記熱処理を100〜110℃で行う請求項1に記載の半導体装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005131009A JP4556757B2 (ja) | 2004-06-23 | 2005-04-28 | 半導体装置の製造方法 |
US11/153,898 US7314834B2 (en) | 2004-06-23 | 2005-06-16 | Semiconductor device fabrication method |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004185544 | 2004-06-23 | ||
JP2005131009A JP4556757B2 (ja) | 2004-06-23 | 2005-04-28 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006041477A JP2006041477A (ja) | 2006-02-09 |
JP4556757B2 true JP4556757B2 (ja) | 2010-10-06 |
Family
ID=35906090
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005131009A Expired - Fee Related JP4556757B2 (ja) | 2004-06-23 | 2005-04-28 | 半導体装置の製造方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US7314834B2 (ja) |
JP (1) | JP4556757B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9544997B2 (en) | 2013-03-01 | 2017-01-10 | Panasonic Corporation | Multi-layered film, electronic device, and manufacturing methods thereof |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100663624B1 (ko) * | 2004-04-29 | 2007-01-02 | 엘지.필립스 엘시디 주식회사 | 액정표시장치 제조방법 |
US20070134943A2 (en) * | 2006-04-02 | 2007-06-14 | Dunnrowicz Clarence J | Subtractive - Additive Edge Defined Lithography |
JP5407316B2 (ja) * | 2008-12-12 | 2014-02-05 | パナソニック株式会社 | 半導体装置の製造方法 |
KR101056900B1 (ko) | 2010-07-09 | 2011-08-12 | 주식회사 하이닉스반도체 | 미세 패턴 형성 방법 |
CN104377117A (zh) * | 2014-09-26 | 2015-02-25 | 中国科学院半导体研究所 | 利用相对易腐蚀的金属制备另一种金属图形的剥离方法 |
US20190035906A1 (en) * | 2016-01-27 | 2019-01-31 | National Institute Of Advanced Industrial Science And Technology | Field Effect Transistor and Method for Manufacturing Same |
TWI717829B (zh) * | 2019-09-10 | 2021-02-01 | 國立交通大學 | 製造iii-v族半導體裝置的互連件之方法,及iii-v族半導體裝置 |
CN113764261B (zh) * | 2020-10-15 | 2023-08-22 | 腾讯科技(深圳)有限公司 | 空桥结构及其制作方法、超导量子芯片及其制作方法 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61245531A (ja) * | 1985-04-23 | 1986-10-31 | Seiko Epson Corp | 薄膜のパタ−ニング方法 |
JPH0446346A (ja) * | 1990-06-14 | 1992-02-17 | Toshiba Corp | 半導体装置の製造方法 |
JPH05206025A (ja) * | 1992-01-27 | 1993-08-13 | Rohm Co Ltd | 微細加工方法 |
JPH0729846A (ja) * | 1993-07-15 | 1995-01-31 | Honda Motor Co Ltd | 半導体装置の電極形成方法 |
JPH0950133A (ja) * | 1995-08-09 | 1997-02-18 | Fuji Elelctrochem Co Ltd | レジスト形成方法 |
JPH10154707A (ja) * | 1996-09-27 | 1998-06-09 | Hitachi Cable Ltd | 半導体装置の製造方法 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4224361A (en) * | 1978-09-05 | 1980-09-23 | International Business Machines Corporation | High temperature lift-off technique |
US5120622A (en) * | 1990-02-05 | 1992-06-09 | Eastman Kodak Company | Lift-off process for patterning dichroic filters |
JP3119957B2 (ja) * | 1992-11-30 | 2000-12-25 | 株式会社東芝 | 半導体装置の製造方法 |
TW594395B (en) * | 2000-09-29 | 2004-06-21 | Nippon Zeon Co | Photoresist composition for insulating film, insulating film for organic electroluminescent element, and process for producing the same |
-
2005
- 2005-04-28 JP JP2005131009A patent/JP4556757B2/ja not_active Expired - Fee Related
- 2005-06-16 US US11/153,898 patent/US7314834B2/en not_active Expired - Fee Related
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61245531A (ja) * | 1985-04-23 | 1986-10-31 | Seiko Epson Corp | 薄膜のパタ−ニング方法 |
JPH0446346A (ja) * | 1990-06-14 | 1992-02-17 | Toshiba Corp | 半導体装置の製造方法 |
JPH05206025A (ja) * | 1992-01-27 | 1993-08-13 | Rohm Co Ltd | 微細加工方法 |
JPH0729846A (ja) * | 1993-07-15 | 1995-01-31 | Honda Motor Co Ltd | 半導体装置の電極形成方法 |
JPH0950133A (ja) * | 1995-08-09 | 1997-02-18 | Fuji Elelctrochem Co Ltd | レジスト形成方法 |
JPH10154707A (ja) * | 1996-09-27 | 1998-06-09 | Hitachi Cable Ltd | 半導体装置の製造方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9544997B2 (en) | 2013-03-01 | 2017-01-10 | Panasonic Corporation | Multi-layered film, electronic device, and manufacturing methods thereof |
Also Published As
Publication number | Publication date |
---|---|
JP2006041477A (ja) | 2006-02-09 |
US7314834B2 (en) | 2008-01-01 |
US20060138078A1 (en) | 2006-06-29 |
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