JP4544876B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP4544876B2
JP4544876B2 JP2004026534A JP2004026534A JP4544876B2 JP 4544876 B2 JP4544876 B2 JP 4544876B2 JP 2004026534 A JP2004026534 A JP 2004026534A JP 2004026534 A JP2004026534 A JP 2004026534A JP 4544876 B2 JP4544876 B2 JP 4544876B2
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JP
Japan
Prior art keywords
semiconductor wafer
wet etching
semiconductor
wiring
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2004026534A
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English (en)
Japanese (ja)
Other versions
JP2004282035A5 (https=
JP2004282035A (ja
Inventor
彰 鈴木
崇 野間
裕之 篠木
幸弘 高尾
眞三 石部
茂樹 大塚
恵一 山口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP2004026534A priority Critical patent/JP4544876B2/ja
Priority to TW093104415A priority patent/TWI233669B/zh
Priority to US10/784,888 priority patent/US7371693B2/en
Priority to KR1020040012208A priority patent/KR100661042B1/ko
Priority to EP04004219A priority patent/EP1453090A3/en
Priority to CNB200410006626XA priority patent/CN100355036C/zh
Publication of JP2004282035A publication Critical patent/JP2004282035A/ja
Publication of JP2004282035A5 publication Critical patent/JP2004282035A5/ja
Priority to US12/051,502 priority patent/US7981807B2/en
Application granted granted Critical
Publication of JP4544876B2 publication Critical patent/JP4544876B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • E—FIXED CONSTRUCTIONS
    • E06—DOORS, WINDOWS, SHUTTERS, OR ROLLER BLINDS IN GENERAL; LADDERS
    • E06B—FIXED OR MOVABLE CLOSURES FOR OPENINGS IN BUILDINGS, VEHICLES, FENCES OR LIKE ENCLOSURES IN GENERAL, e.g. DOORS, WINDOWS, BLINDS, GATES
    • E06B3/00—Window sashes, door leaves, or like elements for closing wall or like openings; Layout of fixed or moving closures, e.g. windows in wall or like openings; Features of rigidly-mounted outer frames relating to the mounting of wing frames
    • E06B3/96—Corner joints or edge joints for windows, doors, or the like frames or wings
    • E06B3/964—Corner joints or edge joints for windows, doors, or the like frames or wings using separate connection pieces, e.g. T-connection pieces
    • E06B3/968—Corner joints or edge joints for windows, doors, or the like frames or wings using separate connection pieces, e.g. T-connection pieces characterised by the way the connecting pieces are fixed in or on the frame members
    • E06B3/9687—Corner joints or edge joints for windows, doors, or the like frames or wings using separate connection pieces, e.g. T-connection pieces characterised by the way the connecting pieces are fixed in or on the frame members with screws blocking the connecting piece inside or on the frame member
    • E06B3/9688—Mitre joints
    • E—FIXED CONSTRUCTIONS
    • E06—DOORS, WINDOWS, SHUTTERS, OR ROLLER BLINDS IN GENERAL; LADDERS
    • E06B—FIXED OR MOVABLE CLOSURES FOR OPENINGS IN BUILDINGS, VEHICLES, FENCES OR LIKE ENCLOSURES IN GENERAL, e.g. DOORS, WINDOWS, BLINDS, GATES
    • E06B3/00—Window sashes, door leaves, or like elements for closing wall or like openings; Layout of fixed or moving closures, e.g. windows in wall or like openings; Features of rigidly-mounted outer frames relating to the mounting of wing frames
    • E06B3/96—Corner joints or edge joints for windows, doors, or the like frames or wings
    • E06B3/964—Corner joints or edge joints for windows, doors, or the like frames or wings using separate connection pieces, e.g. T-connection pieces
    • E06B3/9647—Corner joints or edge joints for windows, doors, or the like frames or wings using separate connection pieces, e.g. T-connection pieces the connecting piece being part of or otherwise linked to the window or door fittings
    • E06B3/9648—Mitre joints
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/129—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed forming a chip-scale package [CSP]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/656—Fan-in layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H10W72/01331—Manufacture or treatment of die-attach connectors using blanket deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding

Landscapes

  • Engineering & Computer Science (AREA)
  • Civil Engineering (AREA)
  • Structural Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Dicing (AREA)
  • Solid State Image Pick-Up Elements (AREA)
JP2004026534A 2003-02-25 2004-02-03 半導体装置の製造方法 Expired - Fee Related JP4544876B2 (ja)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP2004026534A JP4544876B2 (ja) 2003-02-25 2004-02-03 半導体装置の製造方法
TW093104415A TWI233669B (en) 2003-02-25 2004-02-23 Method for making a semiconductor device
KR1020040012208A KR100661042B1 (ko) 2003-02-25 2004-02-24 반도체 장치의 제조 방법
US10/784,888 US7371693B2 (en) 2003-02-25 2004-02-24 Manufacturing method of semiconductor device with chamfering
EP04004219A EP1453090A3 (en) 2003-02-25 2004-02-25 Manufacturing method of semiconductor device
CNB200410006626XA CN100355036C (zh) 2003-02-25 2004-02-25 半导体装置的制造方法
US12/051,502 US7981807B2 (en) 2003-02-25 2008-03-19 Manufacturing method of semiconductor device with smoothing

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2003046755 2003-02-25
JP2004026534A JP4544876B2 (ja) 2003-02-25 2004-02-03 半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2004282035A JP2004282035A (ja) 2004-10-07
JP2004282035A5 JP2004282035A5 (https=) 2007-03-15
JP4544876B2 true JP4544876B2 (ja) 2010-09-15

Family

ID=32775226

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004026534A Expired - Fee Related JP4544876B2 (ja) 2003-02-25 2004-02-03 半導体装置の製造方法

Country Status (6)

Country Link
US (2) US7371693B2 (https=)
EP (1) EP1453090A3 (https=)
JP (1) JP4544876B2 (https=)
KR (1) KR100661042B1 (https=)
CN (1) CN100355036C (https=)
TW (1) TWI233669B (https=)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4401066B2 (ja) * 2002-11-19 2010-01-20 三洋電機株式会社 半導体集積装置及びその製造方法
JP4322181B2 (ja) * 2004-07-29 2009-08-26 三洋電機株式会社 半導体装置の製造方法
US7049208B2 (en) * 2004-10-11 2006-05-23 Intel Corporation Method of manufacturing of thin based substrate
US7371676B2 (en) 2005-04-08 2008-05-13 Micron Technology, Inc. Method for fabricating semiconductor components with through wire interconnects
US7393770B2 (en) * 2005-05-19 2008-07-01 Micron Technology, Inc. Backside method for fabricating semiconductor components with conductive interconnects
JP4544143B2 (ja) * 2005-06-17 2010-09-15 セイコーエプソン株式会社 半導体装置の製造方法、半導体装置、回路基板及び電子機器
JP2007012995A (ja) * 2005-07-01 2007-01-18 Toshiba Corp 超小型カメラモジュール及びその製造方法
JP2009512213A (ja) * 2005-10-11 2009-03-19 ボク，タエソック シリコン・バイア・コンタクトを利用したシーモス・イメージセンサーのウェハー・レべル・パッケージおよびその製造方法
US7307348B2 (en) * 2005-12-07 2007-12-11 Micron Technology, Inc. Semiconductor components having through wire interconnects (TWI)
TW200737506A (en) * 2006-03-07 2007-10-01 Sanyo Electric Co Semiconductor device and manufacturing method of the same
US7659612B2 (en) 2006-04-24 2010-02-09 Micron Technology, Inc. Semiconductor components having encapsulated through wire interconnects (TWI)
US7405139B2 (en) 2006-08-03 2008-07-29 International Business Machines Corporation Prevention of backside cracks in semiconductor chips or wafers using backside film or backside wet etch
TWI367557B (en) * 2006-08-11 2012-07-01 Sanyo Electric Co Semiconductor device and manufaturing method thereof
JP4773307B2 (ja) * 2006-09-15 2011-09-14 Ｏｋｉセミコンダクタ株式会社 半導体装置の製造方法
JP5010247B2 (ja) * 2006-11-20 2012-08-29 オンセミコンダクター・トレーディング・リミテッド 半導体装置及びその製造方法
JP2009032929A (ja) * 2007-07-27 2009-02-12 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JP2009099838A (ja) * 2007-10-18 2009-05-07 Nec Electronics Corp 半導体装置およびその製造方法
GB2459301B (en) * 2008-04-18 2011-09-14 Xsil Technology Ltd A method of dicing wafers to give high die strength
US8710665B2 (en) * 2008-10-06 2014-04-29 Infineon Technologies Ag Electronic component, a semiconductor wafer and a method for producing an electronic component
JP2010103300A (ja) * 2008-10-23 2010-05-06 Sanyo Electric Co Ltd 半導体装置及びその製造方法
EP2446478B1 (en) 2009-06-25 2018-09-12 IMEC vzw Biocompatible packaging
US8212340B2 (en) * 2009-07-13 2012-07-03 Advanced Semiconductor Engineering, Inc. Chip package and manufacturing method thereof
JP2012189396A (ja) * 2011-03-09 2012-10-04 Mitsubishi Electric Corp Ｉｃチップ、半導体部品、検査用プローブ、ハンディマルチテスター、及び通信装置
JP6265594B2 (ja) * 2012-12-21 2018-01-24 ラピスセミコンダクタ株式会社 半導体装置の製造方法、及び半導体装置
KR101440308B1 (ko) * 2013-02-21 2014-09-18 옵토팩 주식회사 반도체 장치 및 그 제조 방법
US11114402B2 (en) * 2018-02-23 2021-09-07 Semiconductor Components Industries, Llc Semiconductor device with backmetal and related methods
JP7384820B2 (ja) * 2018-11-15 2023-11-21 ローム株式会社 半導体装置
JP7056685B2 (ja) * 2020-05-27 2022-04-19 信越半導体株式会社 シリコンウェーハのエッチング方法
CN112053936B (zh) * 2020-09-22 2024-06-11 粤芯半导体技术股份有限公司 晶圆背面粗糙化控制方法以及功率器件制造方法

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54110783A (en) * 1978-02-20 1979-08-30 Hitachi Ltd Semiconductor substrate and its manufacture
JPS59201425A (ja) * 1983-04-28 1984-11-15 Toshiba Corp ウエハ−の裏面加工方法
US4612408A (en) * 1984-10-22 1986-09-16 Sera Solar Corporation Electrically isolated semiconductor integrated photodiode circuits and method
JP2610703B2 (ja) * 1990-09-05 1997-05-14 住友電気工業株式会社 半導体素子の製造方法
JPH0715897B2 (ja) * 1991-11-20 1995-02-22 株式会社エンヤシステム ウエ−ハ端面エッチング方法及び装置
US5268065A (en) * 1992-12-21 1993-12-07 Motorola, Inc. Method for thinning a semiconductor wafer
US5729038A (en) * 1995-12-15 1998-03-17 Harris Corporation Silicon-glass bonded wafers
US5719085A (en) * 1995-09-29 1998-02-17 Intel Corporation Shallow trench isolation technique
US6498074B2 (en) * 1996-10-29 2002-12-24 Tru-Si Technologies, Inc. Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners
US6448153B2 (en) * 1996-10-29 2002-09-10 Tru-Si Technologies, Inc. Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners
IL123207A0 (en) * 1998-02-06 1998-09-24 Shellcase Ltd Integrated circuit device
KR100289403B1 (ko) 1998-05-11 2001-06-01 김영환 반도체패키지제조방법
JP4103255B2 (ja) * 1999-07-02 2008-06-18 ソニー株式会社 半導体デバイスチップ及び半導体デバイスの製造方法
US6326689B1 (en) * 1999-07-26 2001-12-04 Stmicroelectronics, Inc. Backside contact for touchchip
US6350664B1 (en) 1999-09-02 2002-02-26 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method of manufacturing the same
JP2001144123A (ja) * 1999-09-02 2001-05-25 Matsushita Electric Ind Co Ltd 半導体装置の製造方法および半導体装置
JP3368876B2 (ja) * 1999-11-05 2003-01-20 株式会社東京精密 半導体チップ製造方法
IL133453A0 (en) * 1999-12-10 2001-04-30 Shellcase Ltd Methods for producing packaged integrated circuit devices and packaged integrated circuit devices produced thereby
JP2001185519A (ja) * 1999-12-24 2001-07-06 Hitachi Ltd 半導体装置及びその製造方法
US6498387B1 (en) * 2000-02-15 2002-12-24 Wen-Ken Yang Wafer level package and the process of the same
US6720522B2 (en) 2000-10-26 2004-04-13 Kabushiki Kaisha Toshiba Apparatus and method for laser beam machining, and method for manufacturing semiconductor devices using laser beam machining
JP3660294B2 (ja) * 2000-10-26 2005-06-15 株式会社東芝 半導体装置の製造方法
GB2368971B (en) * 2000-11-11 2005-01-05 Pure Wafer Ltd Process for Reclaimimg Wafer Substrates
US6506681B2 (en) * 2000-12-06 2003-01-14 Micron Technology, Inc. Thin flip—chip method
JP2002217194A (ja) * 2001-01-15 2002-08-02 Hitachi Ltd 半導体装置
US6534379B1 (en) * 2001-03-26 2003-03-18 Advanced Micro Devices, Inc. Linerless shallow trench isolation method
JP4669162B2 (ja) * 2001-06-28 2011-04-13 株式会社ディスコ 半導体ウェーハの分割システム及び分割方法
US20030089950A1 (en) * 2001-11-15 2003-05-15 Kuech Thomas F. Bonding of silicon and silicon-germanium to insulating substrates
JP4791693B2 (ja) * 2002-04-11 2011-10-12 積水化学工業株式会社 半導体チップの製造方法
DE60218643D1 (de) * 2002-06-28 2007-04-19 St Microelectronics Srl Herstellungsverfahren für Gräben mit schrägem Profil und gerundeten Oberkanten
US20040169176A1 (en) * 2003-02-28 2004-09-02 Peterson Paul E. Methods of forming thin film transistors and related systems
US20060231829A1 (en) * 2005-04-13 2006-10-19 Xerox Corporation TFT gate dielectric with crosslinked polymer

Also Published As

Publication number Publication date
TW200425428A (en) 2004-11-16
US20040229445A1 (en) 2004-11-18
JP2004282035A (ja) 2004-10-07
EP1453090A3 (en) 2008-06-04
US7371693B2 (en) 2008-05-13
KR100661042B1 (ko) 2006-12-26
EP1453090A2 (en) 2004-09-01
CN1591789A (zh) 2005-03-09
US20080171421A1 (en) 2008-07-17
TWI233669B (en) 2005-06-01
CN100355036C (zh) 2007-12-12
KR20040076623A (ko) 2004-09-01
US7981807B2 (en) 2011-07-19

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