JP4308765B2 - ボンディングワイヤ接続方法 - Google Patents

ボンディングワイヤ接続方法 Download PDF

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JP4308765B2
JP4308765B2 JP2004528420A JP2004528420A JP4308765B2 JP 4308765 B2 JP4308765 B2 JP 4308765B2 JP 2004528420 A JP2004528420 A JP 2004528420A JP 2004528420 A JP2004528420 A JP 2004528420A JP 4308765 B2 JP4308765 B2 JP 4308765B2
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contact
carrier
nail head
head contact
connection
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JP2006502564A (ja
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クラウス ジークリンデ
ラウシャー グンター
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Siemens AG
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Siemens AG
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  • Manufacturing & Machinery (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Description

半導体チップと、貫通接触接続部が設けられた担体と、該半導体チップの接続パッドを該貫通接触接続部に接続するワイヤとを有する回路装置、および該回路装置の製造方法
本発明は、半導体チップと、コンタクト場所が設けられた担体と、該半導体チップの接続パッドを該コンタクト場所に接続するワイヤとを有する回路装置に関する。ここでは、該コンタクト場所に第１のネイルヘッドコンタクトが形成され、該ワイヤの第１の端部は第２のネイルヘッドコンタクトによって該半導体チップの接続パッドに接続され、該ワイヤの第２の端部はウェッジコンタクトによって第１のネイルヘッドコンタクトに接続されている。本発明はさらに、この種の回路装置の製造方法にも関する。
この種の回路装置およびこの種の方法は、ＪＰ２０００３２３５１４Ａから公知である。ここでは良好なボンディングコンタクトを、金との接合性が悪い材料から成る導体路上に形成するという課題を解決しなければならない。このボンディングコンタクトは、とりわけウェッジコンタクトである。別の適用分野は、この公報には示唆されていない。
本発明の課題は、ボンディングすべき場所におけるメタライジングの程度がごく僅かしかない担体表面とワイヤとの接続を可能な限り簡単および低コストにし、かつ良好にすることである。前記ワイヤは、とりわけ金ワイヤまたはアルミニウムワイヤである。
前記課題は、請求項１に記載された回路装置または請求項６に記載された方法によって解決される。有利な発展形態は、従属請求項に記載されている。
それによれば本発明の技術思想は、ネイルヘッドコンタクトを担体表面上に、貫通接触接続部の場所にて、ここに別の表面メタライジング部を設けずに直接取り付けることである。担体を貫通して貫通接触接続部を形成する孔のみがメタライジングされる。担体の表面のこの孔の場所にネイルヘッドコンタクトを取り付けることにより、孔に形成されたメタライジング部との接続が十分に良好になり、該ネイルヘッドコンタクトに取り付けられたウェッジコンタクトによって、担体の別の表面との接続または２つの絶縁性の担体層間の金属層との接続が実現される。すなわち本発明では、担体上のコンタクトパッドの代わりに第１のネイルヘッドコンタクトが代用される。こうすることによって有利には、高価な基板表面が削減され、回路は縮小される。
本発明による回路装置ないしは本発明による方法の別の利点は、担体表面上に設けられる通常のボンディング接続面を省略して、該担体表面上に導体路を製造する際の処理ステップが１つ削減できることである。このことによって、このために通常使用される金ペーストが削減され、コストが低減される。
本発明の発展形態では、担体をセラミックスによって形成しなければならない。択一的に、担体をＰＣボード（printed circuit board）とすることもできる。この担体を絶縁層から形成して、貫通接触接続部を１つの担体表面から別の担体表面に到達させることができる。しかし、担体を２つまたはそれ以上の絶縁層から形成して、該絶縁層間にメタライジング部を導体路および／または質量体表面の形態で配置し、貫通接触接続部を少なくとも部分的に、この中間メタライジング部までのみ到達させることもできる。
本発明を以下で、実施例に基づいて図面を使用して詳細に説明する。
図 本発明による回路装置である。
この図では、２つの絶縁層を有する担体１が形成されており、これらの２つの絶縁層間には、メタライジングされた面および／または導体路２が配置されている。担体１の１つの表面上に、半導体チップ３が配置されている。半導体チップ３が配置された担体層を貫通して貫通接触接続部９が案内されており、この貫通接触接続部９によって、メタライジング面または導体路２が接触接続される。本発明によれば、担体表面にコンタクトパッドは形成されず、その代わりに第１のネイルヘッドコンタクト４が取り付けられ、このネイルヘッドコンタクト４からワイヤは分離されている。半導体チップ３の接続パッド（詳細には図示されていない）上に、第２のネイルヘッドコンタクト５が形成されている。このネイルヘッドコンタクト５から出発して、該半導体チップ３と貫通接触接続部９とを接続するワイヤ６が第１のネイルヘッドコンタクト４まで延在しており、そこでウェッジコンタクト７を使用して、該ネイルヘッドコンタクト４に接続されている。図示されている実施例では、第１のネイルヘッドコンタクト４は担体層の貫通接触接続部９の孔に、ある程度押入されている。こうすることによって、孔のメタライジング部との接触接続が良好になる。
本発明は、中間メタライジング部を有する多層の担体にて適用することに限定されることはなく、裏面メタライジング部を有する単層の担体に適用することもできる。
図中には、本発明による方法を図解するため、ボンディングツールのキャピラリ８も示されている。
本発明による回路装置である。

Claims (3)

  1. 半導体チップ（３）の接続パッドと、セラミックスによって形成されている担体（１）に設けられた貫通接触接続部（９）との電気的な接続を行う製造方法において、
    該担体（１）を貫通して該貫通接触接続部（９）を形成する孔のみがメタライジングされ、
    ・第１のネイルヘッドコンタクト（４）を担体表面上に、前記貫通接触接続部（９）の場所にて、ここに別の表面メタライジング部を設けずに、ボンディングツールのキャピラリによって直接形成するステップと、
    ・該キャピラリ内から該第１のネイルヘッドコンタクト（４）まで繋がっているワイヤ（６）を前記第１のネイルヘッドコンタクト（４）から分離するステップと、
    ・第２のネイルヘッドコンタクト（５）を該半導体チップ（３）の接続パッド上に、該ボンディングツールのキャピラリ（８）によって形成するステップと、
    ・前記ワイヤ（６）を前記第１のネイルヘッドコンタクト（４）まで案内するステップと、
    ・前記ワイヤ（６）の端部とのウェッジコンタクト（７）を前記第１のネイルヘッドコンタクト（４）上に、該ボンディングツールのキャピラリ（８）によって形成するステップを有することを特徴とする製造方法。
  2. 半導体チップ（３）の接続パッドと、多層のＰＣボードによって形成されている担体（１）に設けられた貫通接触接続部（９）との電気的な接続を行う製造方法において、
    該貫通接触接続部（９）は、該担体の表面と２つのＰＣボード層間のメタライジング部（２）とを接続し、
    該担体（１）を貫通して該貫通接触接続部（９）を形成する孔のみがメタライジングされ、
    ・第１のネイルヘッドコンタクト（４）を担体表面上に、前記貫通接触接続部（９）の場所にて、ここに別の表面メタライジング部を設けずに、ボンディングツールのキャピラリによって直接形成するステップと、
    ・該キャピラリ内から該第１のネイルヘッドコンタクト（４）まで繋がっているワイヤ（６）を前記第１のネイルヘッドコンタクト（４）から分離するステップと、
    ・第２のネイルヘッドコンタクト（５）を該半導体チップ（３）の接続パッド上に、該ボンディングツールのキャピラリ（８）によって形成するステップと、
    ・前記ワイヤ（６）を前記第１のネイルヘッドコンタクト（４）まで案内するステップと、
    ・前記ワイヤ（６）の端部とのウェッジコンタクト（７）を前記第１のネイルヘッドコンタクト（４）上に、該ボンディングツールのキャピラリ（８）によって形成するステップを有することを特徴とする製造方法。
  3. 前記担体（１）は多層のセラミックスによって形成されており、
    前記貫通接触接続部（９）は、前記担体の表面と２つのセラミック層間のメタライジング部（２）とを接続する、請求項１記載の製造方法。
JP2004528420A 2002-07-24 2003-07-22 ボンディングワイヤ接続方法 Expired - Fee Related JP4308765B2 (ja)

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PCT/DE2003/002465 WO2004017400A1 (de) 2002-07-24 2003-07-22 Anordnung mit einem halbleiterchip und dessen träger sowie verfahren zur bond-drahtverbindung

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