EP1523769A1 - Anordnung mit einem halbleiterchip und dessen träger sowie verfahren zur bond-drahtverbindung - Google Patents

Anordnung mit einem halbleiterchip und dessen träger sowie verfahren zur bond-drahtverbindung

Info

Publication number
EP1523769A1
EP1523769A1 EP03787714A EP03787714A EP1523769A1 EP 1523769 A1 EP1523769 A1 EP 1523769A1 EP 03787714 A EP03787714 A EP 03787714A EP 03787714 A EP03787714 A EP 03787714A EP 1523769 A1 EP1523769 A1 EP 1523769A1
Authority
EP
European Patent Office
Prior art keywords
contact
carrier
semiconductor chip
nailhead
wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP03787714A
Other languages
English (en)
French (fr)
Inventor
Sieglinde Kraus
Gunther Rauscher
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Continental Automotive GmbH
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP1523769A1 publication Critical patent/EP1523769A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486Via connections through the substrate with or without pins
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/328Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by welding
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007Surface contacts, e.g. bumps
    • H05K3/4015Surface contacts, e.g. bumps using auxiliary conductive elements, e.g. pieces of metal foil, metallic spheres
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48095Kinked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48235Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a via metallisation of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48475Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
    • H01L2224/48476Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area
    • H01L2224/48477Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding)
    • H01L2224/48478Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball
    • H01L2224/4848Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball outside the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485Material
    • H01L2224/48505Material at the bonding interface
    • H01L2224/48599Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485Material
    • H01L2224/48505Material at the bonding interface
    • H01L2224/48699Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78Apparatus for connecting with wire connectors
    • H01L2224/7825Means for applying energy, e.g. heating means
    • H01L2224/783Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301Capillary
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009Pre-treatment of the connector or the bonding area
    • H01L2224/85051Forming additional members, e.g. for "wedge-on-ball", "ball-on-wedge", "ball-on-ball" connections
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512Aligning
    • H01L2224/85148Aligning involving movement of a part of the bonding apparatus
    • H01L2224/85169Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
    • H01L2224/8518Translational movements
    • H01L2224/85181Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852Applying energy for connecting
    • H01L2224/85201Compression bonding
    • H01L2224/85205Ultrasonic bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78Apparatus for connecting with wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01027Cobalt [Co]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01032Germanium [Ge]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01068Erbium [Er]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/111Pads for surface mounting, e.g. lay-out
    • H05K1/112Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113Via provided in pad; Pad over filled via
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04Soldering or other types of metallurgic bonding
    • H05K2203/049Wire bonding

Definitions

  • Arrangement comprising a semiconductor chip and a carrier provided with a plated through-hole as well as a wire connecting a connection pad of the semiconductor chip to the plated-through hole, and method for producing such an arrangement
  • the invention relates to an arrangement comprising a semiconductor chip and a carrier provided with a contact point and a wire connecting a terminal pad of the semiconductor chip with the contact point, wherein a first nailhead contact is formed on the contact point, the first end of the. Wire is connected to a second nailhead contact with the terminal pad of the semiconductor chip and the second end of the wire by means of a wedge contact with the first nailhead contact.
  • the invention also relates to a method for producing such an arrangement.
  • the object of the invention is to enable as simple and cost-effective as possible a connection of a wire, in particular a gold or aluminum wire with a carrier surface, which has only a low degree of metallization at the point to be bonded.
  • the invention teaches a nailhead contact directly onto a support surface at the site of a via contact. without further surface metallization being present there. Only the through-hole forming hole through the carrier is metallized. By applying the nailhead contact on the surface of the carrier at the location of this hole, a sufficiently good connection is made to the metallization in the hole, so that by means of the Wedge contact applied to the nailhead contact, a connection to the other surface of the carrier or to a metal layer between two insulating carrier layers is made. Thus, a contact pad on the carrier is replaced in accordance with the invention by the first nailhead contact. This advantageously saves expensive substrate area; the circuit can be switched off.
  • a further advantage of the arrangement according to the invention or of the method according to the invention is that, by dispensing with the customary bonding pads on the carrier surface, a process step in the production of printed conductors on the carrier surface can be dispensed with. This leads to a cost reduction due to the saving of gold paste commonly used for this purpose.
  • the carrier is to be formed with a ceramic.
  • the carrier may also be a PC board (printed circuit board).
  • the carrier may be both of an insulating layer, so that the through-connection extends from one carrier surface to the other, but it may also consist of two or more insulating layers, wherein metallizations in the form of lines and / or ground planes are arranged between the layers and the vias at least partially extend only to these intermetallicizations.
  • FIG. 1 An arrangement according to the invention.
  • a carrier 1 is formed with two insulating layers, between which metallized surfaces and / or conductor tracks 2 are arranged.
  • a semiconductor chip 3 is arranged on a surface of the carrier 1.
  • the carrier layer, on which the semiconductor chip 3 is arranged leads a through-connection 9, by means of which the metallized surface o- of the conductor track 2 can be contacted.
  • no contact pad is provided on the carrier surface but a first nailhead contact 4 is applied, from which the wire has been severed.
  • a connection pad (not shown in detail) of the semiconductor chip 3 is a second
  • Nailhead contact 5 generates, starting from which the semiconductor chip 3 with the through-connection 9 connecting wire 6 to the first nailhead contact 4 extends and is connected there by means of a wedge contact 7 with this.
  • the first nail head contact 4 is pressed somewhat into the hole in the carrier layer of the through-connection 9, so that good contact with the metallization of the hole is achieved.
  • the invention is not limited to multi-layer application
  • the capillary 8 of the bonding tool is also shown to indicate the inventive method.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

Auf einem Träger (1) ist ein Halbleiterchip (3) angeordnet, der mit einer metallisierten Fläche auf er Rückseite des Trägers über eine Durchkontaktierung (9) verbunden ist. Auf der Durchkontaktierung (9) ist ein erster Nailhead-Kontakt (4) erzeugt, von dem der Draht abgetrennt wurde. Auf einem Anschlusspad des Halbleiterchips (3) ist ein zweiter Nailhead-Kontakt (5) erzeugt, von dem ausgehend der den Halbleiterchip (3) mit der Durchkontaktierung (9) verbindende Draht (6) zum ersten Nailhead-Kontakt (4) verläuft und dort mittels eines Wedge-Kontakts (7) mit diesem verbunden ist.

Description

ANORDNUNG MIT EINEM HALBLEITERCHIP UND DESSEN TRÄGER SOWIE VERFAHREN ZUR BOND-DRAHTVERBINDUNG
Beschreibung
Anordnung mit einem Halbleiterchip und einem mit einer Durchkontaktierung versehenen Träger sowie einem ein Anschlusspad des Halbleiterchips mit der Durchkontaktierung verbindenden Draht und Verfahren zum Herstellen einer solchen Anordnung
Die Erfindung betrifft eine Anordnung mit einem Halbleiterchip und einem mit einer Kontaktstelle versehenen Träger so- wie einem ein Anschlusspad des Halbleiterchips mit der Kontaktstelle verbindenden Draht, wobei auf der Kontaktstelle ein erster Nailhead-Kontakt geformt ist, das erste Ende des . Drahtes mit einem zweiten Nailhead-Kontakt mit dem Anschlusspad des Halbleiterchips und das zweite Ende des Drahtes mittels eines Wedge-Kontaktes mit dem ersten Nailhead-Kontakt verbunden ist. Die Erfindung betrifft außerdem ein Verfahren zum Herstellen einer solchen Anordnung.
Eine solche Anordnung und ein solches Verfahren sind aus der JP 2000-323514 A bekannt. Dort soll das Problem gelöst werden, gute Bondkontakte, insbesondere Wedge-Kontakte, auf Leiterbahnen aus sich schlecht mit Gold verbindenden Materialien herzustellen. Weitere Anwendungsgebiete sind dieser Schrift nicht zu entnehmen.
Die Aufgabe der Erfindung ist es, eine möglichst einfache und kostengünstige und trotzdem gute Verbindung eines Drahtes, insbesondere eines Gold- oder Aluminiumdrahtes mit einer Trägeroberfläche, die an der zu bondenden Stelle nur einen ge- ringen Metallisierungsgrad aufweist, zu ermöglichen.
Die Aufgabe wird durch die Anordnung gemäß Anspruch 1 oder das Verfahren gemäß Anspruch 6 gelöst. Vorteilhafte Weiterbildungen sind in den Unteransprüchen angegeben.
Demnach lehrt die Erfindung, einen Nailhead-Kontakt direkt auf eine Trägeroberfläche an der Stelle einer Durchkontaktie- rung anzubringen, ohne dass dort eine weitere Oberflächenme- tallisierung vorhanden ist. Lediglich das die Durchkontaktierung bildende Loch durch den Träger ist metallisiert. Durch das Aufbringen des Nailhead-Kontaktes auf der Oberfläche des Trägers an der Stelle dieses Lochs wird eine ausreichend gute Verbindung zu der Metallisierung im Loch hergestellt, so dass mittels des auf den Nailhead-Kontakt aufgebrachten Wedge- Kontakts eine Verbindung zur anderen Oberfläche des Trägers oder zu einer Metalllage zwischen zwei isolierenden Träger- schichten hergestellt ist. Es wird also ein Kontaktpad auf dem Träger in erfindungsgemäßer Weise durch den ersten Nailhead-Kontakt ersetzt. Hierdurch wird in vorteilhafter Weise teuere Substratfläche eingespart; die Schaltung kann gesh- rinkt werden.
Ein weiterer Vorteil der erfindungsgemäßen Anordnung bzw. des erfindungsgemäßen Verfahrens ist, dass durch den Verzicht auf die üblichen Bondanschlussflächen auf der Trägeroberfläche ein Prozessschritt bei der Herstellung von Leiterbahnen auf der Trägeroberfläche eingespart werden kann. Dies führt zu einer Kostenreduzierung aufgrund der Einsparung von hierzu üblicherweise verwendeter Goldpaste.
In Weiterbildung der Erfindung soll der Träger mit einer Ke- ramik gebildet sein. Alternativ kann der Träger auch ein PC- Board (printed circuit board) sein. Der Träger kann sowohl aus einer isolierenden Lage sein, so dass die Durchkontaktierung von einer Trägeroberfläche zur anderen reicht, er kann jedoch auch aus zwei oder mehreren isolierenden Lagen beste- hen, wobei zwischen den Lagen Metallisierungen in Form von Leitungen und/oder Masseflächen angeordnet sind und die Durchkontaktierungen zumindest teilweise nur bis zu diesen Zwischenmetallisierungen reichen.
Die Erfindung wird nachfolgend anhand eines Ausführungsbei- spiels mit Hilfe einer Figur näher erläutert. Dabei zeigt die
Figur eine erfindungsgemäße Anordnung.
In der Figur ist ein Träger 1 mit zwei isolierenden Schichten gebildet, zwischen denen metallisierte Flächen und/oder Leiterbahnen 2 angeordnet sind. Auf einer Oberfläche des Trägers 1 ist ein Halbleiterchip 3 angeordnet. Durch die Trägerlage, auf der der Halbleiterchip 3 angeordnet ist, führt eine Durchkontaktierung 9, mittels der die metallisierte Fläche o- der Leiterbahn 2 kontaktiert werden kann. In erfindungsgemäßer Weise ist auf der Trägeroberfläche kein Kontaktpad vorgesehen sondern ein erster Nailhead-Kontakt 4 aufgebracht, von dem der Draht abgetrennt wurde. Auf einem Anschlusspad (nicht näher dargestellt) des Halbleiterchips 3 ist ein zweiter
Nailhead-Kontakt 5 erzeugt, von dem ausgehend der den Halbleiterchip 3 mit der Durchkontaktierung 9 verbindende Draht 6 zum ersten Nailhead-Kontakt 4 verläuft und dort mittels eines Wedge-Kontakts 7 mit diesem verbunden ist. Der erste Nail- head-Kontakt 4 ist im dargestellten Beispiel etwas in das Loch in der Trägerlage der Durchkontaktierung 9 hineingedrückt, so dass ein guter Kontakt mit der Metallisierung des Lochs zustande kommt.
Die Erfindung ist nicht auf die Anwendung bei mehrlagigen
Trägern mit Zwischenmetallisierungen beschränkt sondern lässt sich auch auf einlagige Träger mit Rückseitenmetallisierung anwenden .
In der Figur ist außerdem die Kapillare 8 des Bondwerkzeugs dargestellt, um das erfindungsgemäße Verfahren anzudeuten.

Claims

Patentansprüche
1. Anordnung mit einem Halbleiterchip (3) und einem mit einer Kontaktstelle versehenen Träger (1) sowie einem ein Anschlusspad des Halbleiterchips (3) mit der Kontaktstelle verbindenden Draht (6) , wobei auf der Kontaktstelle ein erster Nailhead-Kontakt (4) geformt ist, das erste Ende des Drahtes (6) mit einem zweiten Nailhead-Kontakt (5) mit dem Anschlusspad des Halbleiterchips (3) und das zweite Ende des Drahtes (6) mittels eines Wedge-Kontaktes (7) mit dem ersten Nailhead-Kontakt (5) verbunden ist, dadurch gekennzeichnet, dass die Kontaktstelle eine Durchkontaktierung (9) im Träger (1) ist und der erste Nailhead-Kontakt (4) direkt auf der Trägeroberfläche an der Stelle der Durchkontaktierung (9) angebracht ist, ohne dass dort eine weitere Oberflächenmetallisierung vorhanden ist.
2. Anordnung nach Anspruch 1, dadurch gekennzeichnet, dass der Träger (1) mit einer Keramik gebildet ist.
3. Anordnung nach Anspruch 1 oder 2 , dadurch gekennzeichnet , dass der Träger (1) mit einer mehrlagigen Keramik gebildet ist und die Durchkontaktierung (9) eine Oberfläche des Trä- gers mit einer Metallisierung (2) zwischen zwei Keramiklagen verbindet .
4. Anordnung nach Anspruch 1, dadurch gekennzeichnet, dass der Träger (1) ein PC-Board ist.
5. Anordnung nach Anspruch 1 oder 4 , dadurch gekennzeichnet, dass der Träger (1) mit einem mehrlagigen PC-Board gebildet ist und die Durchkontaktierung (9) eine Oberfläche des Trägers mit einer Metallisierung (2) zwischen zwei PC-Board- Lagen verbindet.
6. Verfahren zum elektrischen Verbinden eines Anschlusspads eines Halbleiterchips (3) mit einer Durchkontaktierung (9) auf einem Träger (1) mit den Schritten:
• Formen eines ersten Nailhead-Kontaktes (4) direkt auf der Trägeroberfläche an der Stelle der Durchkontaktierung (9), ohne dass dort eine weitere Oberflächenmetallisierung vorhanden ist, mittels der Kapillare eines Bondwerkzeugs,
• Abtrennen des Drahtes (6) von dem ersten Nailhead-Kontakt
(4) , • Formen eines zweiten Nailhead-Kontaktes (5) auf dem
Anschlusspad des Halbleiterchips (3) mittels der Kapillare (8) des Bondwerkzeugs,
• Führen des Drahtes (6) zum ersten Nailhead-Kontakt (4),
• Formen eines Wedge-Kontaktes (7) mit dem Ende des Drahtes (6) auf dem ersten Nailhead-Kontakt (4) mittels der Kapillare (8) des Bondwerkzeugs.
EP03787714A 2002-07-24 2003-07-22 Anordnung mit einem halbleiterchip und dessen träger sowie verfahren zur bond-drahtverbindung Withdrawn EP1523769A1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10233607A DE10233607B4 (de) 2002-07-24 2002-07-24 Anordnung mit einem Halbleiterchip und einem mit einer Durchkontaktierung versehenen Träger sowie einem ein Anschlusspad des Halbleiterchips mit der Durchkontaktierung verbindenden Draht und Verfahren zum Herstellen einer solchen Anordnung
DE10233607 2002-07-24
PCT/DE2003/002465 WO2004017400A1 (de) 2002-07-24 2003-07-22 Anordnung mit einem halbleiterchip und dessen träger sowie verfahren zur bond-drahtverbindung

Publications (1)

Publication Number Publication Date
EP1523769A1 true EP1523769A1 (de) 2005-04-20

Family

ID=30128330

Family Applications (1)

Application Number Title Priority Date Filing Date
EP03787714A Withdrawn EP1523769A1 (de) 2002-07-24 2003-07-22 Anordnung mit einem halbleiterchip und dessen träger sowie verfahren zur bond-drahtverbindung

Country Status (6)

Country Link
US (1) US7053489B2 (de)
EP (1) EP1523769A1 (de)
JP (1) JP4308765B2 (de)
AU (1) AU2003258458A1 (de)
DE (1) DE10233607B4 (de)
WO (1) WO2004017400A1 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070216026A1 (en) * 2006-03-20 2007-09-20 Adams Zhu Aluminum bump bonding for fine aluminum wire
US8021931B2 (en) * 2006-12-11 2011-09-20 Stats Chippac, Inc. Direct via wire bonding and method of assembling the same
US20080191367A1 (en) * 2007-02-08 2008-08-14 Stats Chippac, Ltd. Semiconductor package wire bonding
DE102015221979A1 (de) * 2015-11-09 2017-05-11 Robert Bosch Gmbh Kontaktieranordnung für ein Leiterplattensubstrat und Verfahren zum Kontaktieren eines Leiterplattensubstrats
DE102016109349A1 (de) * 2016-05-20 2017-11-23 Infineon Technologies Ag Chipgehäuse, verfahren zum bilden eines chipgehäuses und verfahren zum bilden eines elektrischen kontakts

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60136356A (ja) * 1983-12-26 1985-07-19 Hitachi Ltd 半導体装置
US4868634A (en) * 1987-03-13 1989-09-19 Citizen Watch Co., Ltd. IC-packaged device
US5258647A (en) * 1989-07-03 1993-11-02 General Electric Company Electronic systems disposed in a high force environment
JP2757574B2 (ja) * 1991-03-14 1998-05-25 日本電気株式会社 低誘電率ハイブリッド多層セラミック配線基板の製造方法
JPH0636356A (ja) * 1992-07-22 1994-02-10 Hitachi Ltd 光ディスク原盤の製造方法
DE4318061C2 (de) * 1993-06-01 1998-06-10 Schulz Harder Juergen Verfahren zum Herstellen eines Metall-Keramik-Substrates
US6111306A (en) * 1993-12-06 2000-08-29 Fujitsu Limited Semiconductor device and method of producing the same and semiconductor device unit and method of producing the same
US5874354A (en) * 1995-09-26 1999-02-23 Siemens Aktiengesellschaft Method for electrically connecting a semiconductor chip to at least one contact surface and smart card module and smart card produced by the method
JPH09330943A (ja) * 1996-06-13 1997-12-22 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
JP3344235B2 (ja) * 1996-10-07 2002-11-11 株式会社デンソー ワイヤボンディング方法
US6133072A (en) * 1996-12-13 2000-10-17 Tessera, Inc. Microelectronic connector with planar elastomer sockets
JP3042441B2 (ja) * 1997-03-12 2000-05-15 日本電気株式会社 低温焼成ガラスセラミックス基板とその製造方法
KR100309957B1 (ko) * 1997-09-08 2002-08-21 신꼬오덴기 고교 가부시키가이샤 반도체장치
DE19809081A1 (de) * 1998-03-04 1999-09-16 Bosch Gmbh Robert Verfahren und Kontaktstelle zur Herstellung einer elektrischen Verbindung
JP2000068309A (ja) * 1998-08-21 2000-03-03 Misuzu Kogyo:Kk 半導体装置の実装方法
JP2000133672A (ja) * 1998-10-28 2000-05-12 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
JP3855532B2 (ja) * 1999-05-12 2006-12-13 株式会社デンソー Icチップと回路基板との接続方法
US6465882B1 (en) * 2000-07-21 2002-10-15 Agere Systems Guardian Corp. Integrated circuit package having partially exposed conductive layer
JP3854054B2 (ja) * 2000-10-10 2006-12-06 株式会社東芝 半導体装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO2004017400A1 *

Also Published As

Publication number Publication date
AU2003258458A1 (en) 2004-03-03
JP4308765B2 (ja) 2009-08-05
DE10233607A1 (de) 2004-02-12
WO2004017400A1 (de) 2004-02-26
DE10233607B4 (de) 2005-09-29
JP2006502564A (ja) 2006-01-19
US20050127497A1 (en) 2005-06-16
US7053489B2 (en) 2006-05-30

Similar Documents

Publication Publication Date Title
DE10352946B4 (de) Halbleiterbauteil mit Halbleiterchip und Umverdrahtungslage sowie Verfahren zur Herstellung desselben
DE10018358B4 (de) Halbleiter-Bauteil und dessen Herstellungsverfahren
DE19755954B4 (de) Leiterrahmenstruktur, diese verwendende Halbleiterbaugruppe und Herstellungsverfahren hierfür
DE102006015447B4 (de) Leistungshalbleiterbauelement mit einem Leistungshalbleiterchip und Verfahren zur Herstellung desselben
DE102006056363B4 (de) Halbleitermodul mit mindestens zwei Substraten und Verfahren zur Herstellung eines Halbleitermoduls mit zwei Substraten
DE10015744A1 (de) Ummantelte elektrische Verbindung für eine Anschlußstruktur
DE102006033222B4 (de) Modul mit flachem Aufbau und Verfahren zur Bestückung
DE69723801T2 (de) Herstellungsverfahren einer Kontaktgitter-Halbleiterpackung
DE10233607B4 (de) Anordnung mit einem Halbleiterchip und einem mit einer Durchkontaktierung versehenen Träger sowie einem ein Anschlusspad des Halbleiterchips mit der Durchkontaktierung verbindenden Draht und Verfahren zum Herstellen einer solchen Anordnung
DE19702186C2 (de) Verfahren zur Gehäusung von integrierten Schaltkreisen
EP2133915A1 (de) Halbleiteranordnung mit besonders gestalteten Bondleitungen und Verfahren zum Herstellen einer solchen Anordnung
EP2067390B1 (de) Verfahren zur herstellung einer anordnung optoelektronischer bauelemente und anordnung optoelektronischer bauelemente
DE10302022B4 (de) Verfahren zur Herstellung eines verkleinerten Chippakets
WO2008138531A1 (de) Kontaktloses übertragungssystem und verfahren zum herstellen desselben
DE102007002807B4 (de) Chipanordnung
WO2006000291A1 (de) Verfahren zur herstellung einer keramischen leiterplatte
WO1997006557A1 (de) Kontakthöckerloses chipkontaktierungsverfahren und damit hergestellte elektronische schaltung
WO2007014800A1 (de) Chipmodul zum einbau in sensorchipkarten für fluidische anwendungen sowie verfahren zur herstellung eines derartigen chipmoduls
DE102005001590B4 (de) BOC-Package
DE102012207560B4 (de) Verfahren zur herstellung und zum betrieb eines halbleitermoduls
EP3611761A1 (de) Verfahren und metallsubstrat zum kontaktieren eines leistungshalbleiters durch ein kontaktierungsmittel mit zumindest einem kontaktierungsfreien bereich als belastungsreduzierende struktur
DE10339762B4 (de) Chipstapel von Halbleiterchips und Verfahren zur Herstellung desselben
DE10330754B4 (de) Verfahren zur Herstellung einer elektrischen Schaltung
WO2016198526A1 (de) Optoelektronische leuchtvorrichtung
DE102022100270A1 (de) Leiterplatte und verfahren zum fertigen von leiterplatte

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20041203

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PT RO SE SI SK TR

AX Request for extension of the european patent

Extension state: AL LT LV MK

DAX Request for extension of the european patent (deleted)
RBV Designated contracting states (corrected)

Designated state(s): FR IT

REG Reference to a national code

Ref country code: DE

Ref legal event code: 8566

17Q First examination report despatched

Effective date: 20060721

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: CONTINENTAL AUTOMOTIVE GMBH

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20110201