JP4306821B2 - 半導体記憶装置 - Google Patents

半導体記憶装置 Download PDF

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Publication number
JP4306821B2
JP4306821B2 JP27443797A JP27443797A JP4306821B2 JP 4306821 B2 JP4306821 B2 JP 4306821B2 JP 27443797 A JP27443797 A JP 27443797A JP 27443797 A JP27443797 A JP 27443797A JP 4306821 B2 JP4306821 B2 JP 4306821B2
Authority
JP
Japan
Prior art keywords
mos transistor
potential
current
gate
channel mos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP27443797A
Other languages
English (en)
Japanese (ja)
Other versions
JPH11111946A5 (enExample
JPH11111946A (ja
Inventor
靖彦 月川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP27443797A priority Critical patent/JP4306821B2/ja
Priority to US09/045,834 priority patent/US5982705A/en
Priority to TW087106768A priority patent/TW374923B/zh
Priority to DE19820040A priority patent/DE19820040B4/de
Priority to KR1019980020816A priority patent/KR100296612B1/ko
Publication of JPH11111946A publication Critical patent/JPH11111946A/ja
Publication of JPH11111946A5 publication Critical patent/JPH11111946A5/ja
Application granted granted Critical
Publication of JP4306821B2 publication Critical patent/JP4306821B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
  • Logic Circuits (AREA)
JP27443797A 1997-10-07 1997-10-07 半導体記憶装置 Expired - Fee Related JP4306821B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP27443797A JP4306821B2 (ja) 1997-10-07 1997-10-07 半導体記憶装置
US09/045,834 US5982705A (en) 1997-10-07 1998-03-23 Semiconductor memory device permitting large output current from output buffer
TW087106768A TW374923B (en) 1997-10-07 1998-05-01 Semiconductor memory device
DE19820040A DE19820040B4 (de) 1997-10-07 1998-05-05 Halbleiterspeichervorrichtung
KR1019980020816A KR100296612B1 (ko) 1997-10-07 1998-06-05 출력버퍼의출력전류를크게할수있는반도체기억장치

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27443797A JP4306821B2 (ja) 1997-10-07 1997-10-07 半導体記憶装置

Publications (3)

Publication Number Publication Date
JPH11111946A JPH11111946A (ja) 1999-04-23
JPH11111946A5 JPH11111946A5 (enExample) 2005-06-16
JP4306821B2 true JP4306821B2 (ja) 2009-08-05

Family

ID=17541675

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27443797A Expired - Fee Related JP4306821B2 (ja) 1997-10-07 1997-10-07 半導体記憶装置

Country Status (5)

Country Link
US (1) US5982705A (enExample)
JP (1) JP4306821B2 (enExample)
KR (1) KR100296612B1 (enExample)
DE (1) DE19820040B4 (enExample)
TW (1) TW374923B (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3765163B2 (ja) * 1997-07-14 2006-04-12 ソニー株式会社 レベルシフト回路
IT1298819B1 (it) * 1998-03-27 2000-02-02 Sgs Thomson Microelectronics Circuito di commutazione
JP3502330B2 (ja) * 2000-05-18 2004-03-02 Ｎｅｃマイクロシステム株式会社 出力回路
JP2002032990A (ja) * 2000-07-17 2002-01-31 Mitsubishi Electric Corp 半導体記憶装置
JP2002076879A (ja) * 2000-09-04 2002-03-15 Mitsubishi Electric Corp 半導体装置
DE10055242C1 (de) * 2000-11-08 2002-02-21 Infineon Technologies Ag Schaltungsanordnung mit interner Versorgungsspannung
JP2006059910A (ja) * 2004-08-18 2006-03-02 Fujitsu Ltd 半導体装置
JP2007035672A (ja) 2005-07-22 2007-02-08 Renesas Technology Corp 半導体集積回路装置
KR102555109B1 (ko) 2021-05-18 2023-07-17 신성환 지주 시설물용 까치집 방지기구

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60201591A (ja) * 1984-03-26 1985-10-12 Hitachi Ltd 半導体集積回路装置
JPH04341997A (ja) * 1991-05-20 1992-11-27 Mitsubishi Electric Corp 半導体メモリ装置
JPH05347386A (ja) * 1992-02-21 1993-12-27 Sony Corp 半導体装置
JPH0774616A (ja) * 1993-07-06 1995-03-17 Seiko Epson Corp 信号電圧レベル変換回路及び出力バッファ回路
KR960004567B1 (ko) * 1994-02-04 1996-04-09 삼성전자주식회사 반도체 메모리 장치의 데이타 출력 버퍼
JPH07230693A (ja) * 1994-02-16 1995-08-29 Toshiba Corp 半導体記憶装置
KR0120565B1 (ko) * 1994-04-18 1997-10-30 김주용 래치-업을 방지한 씨모스형 데이타 출력버퍼
US5543734A (en) * 1994-08-30 1996-08-06 Intel Corporation Voltage supply isolation buffer
JPH09139077A (ja) * 1995-11-17 1997-05-27 Hitachi Ltd ２段ブースト電圧回路、およびこれを用いた半導体メモリ、ならびにこの半導体メモリを用いたコンピュータシステム
JP3738070B2 (ja) * 1995-11-29 2006-01-25 株式会社ルネサステクノロジ 半導体装置

Also Published As

Publication number Publication date
KR19990036519A (ko) 1999-05-25
TW374923B (en) 1999-11-21
DE19820040A1 (de) 1999-04-08
DE19820040B4 (de) 2005-10-27
JPH11111946A (ja) 1999-04-23
KR100296612B1 (ko) 2001-08-07
US5982705A (en) 1999-11-09

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