JP4197660B2 - Mosトランジスタおよびこれを備えた半導体集積回路装置 - Google Patents
Mosトランジスタおよびこれを備えた半導体集積回路装置 Download PDFInfo
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- JP4197660B2 JP4197660B2 JP2004136572A JP2004136572A JP4197660B2 JP 4197660 B2 JP4197660 B2 JP 4197660B2 JP 2004136572 A JP2004136572 A JP 2004136572A JP 2004136572 A JP2004136572 A JP 2004136572A JP 4197660 B2 JP4197660 B2 JP 4197660B2
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- 239000004065 semiconductor Substances 0.000 title claims description 12
- 239000012535 impurity Substances 0.000 claims description 22
- 239000002344 surface layer Substances 0.000 claims description 11
- 230000003071 parasitic effect Effects 0.000 description 31
- 239000000758 substrate Substances 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1087—Substrate region of field-effect devices of field-effect transistors with insulated gate characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
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- H—ELECTRICITY
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- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/02—Casings
- H01F27/022—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/02—Casings
- H01F27/04—Leading of conductors or axles through casings, e.g. for tap-changing arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/08—Cooling; Ventilating
- H01F27/10—Liquid cooling
- H01F27/12—Oil cooling
- H01F27/14—Expansion chambers; Oil conservators; Gas cushions; Arrangements for purifying, drying, or filling
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
図6は、静電保護機能を有するNMOSトランジスタの構造を図解的に示す断面図である。また、図7は、図6に示すNMOSトランジスタの等価回路図である。
この発明によれば、第1導電型エミッタ領域、第2導電型ベース領域および第1導電型領域において、これらの領域をそれぞれエミッタ、ベースおよびコレクタとする縦型トランジスタ(11)が形成される。また、第2導電型ドレイン領域、第1導電型領域および第2導電型ソース領域において、これらの領域をそれぞれコレクタ、ベースおよびエミッタとする寄生トランジスタ(12)が形成される。さらに、第2導電型ドレイン領域において、縦型トランジスタのエミッタ−ベース間抵抗となる寄生抵抗成分(13)が生じ、第1導電型領域において、寄生トランジスタのエミッタ−ベース間抵抗となる寄生抵抗成分(14)が生じる。
図1は、この発明の一実施形態に係るNMOSトランジスタの構造を図解的に示す斜視図である。また、図2は、図1に示すNMOSトランジスタの平面図であり、図3は、図1に示すNMOSトランジスタの等価回路図である。
このNMOSトランジスタは、P型ウエル領域1の表層部に、平面視において、略長方形状のN+型(高濃度N型)ドレイン領域2と、このN+型ドレイン領域2と所定の間隔を空けて、N+型ドレイン領域2の周囲を取り囲む略四角環状のN+型ソース領域3と、このN+型ソース領域3と所定の間隔を空けて、N+型ソース領域3の周囲を取り囲む略四角環状のP+型不純物拡散領域4とが形成されている。N+型ソース領域3およびP+型不純物拡散領域4には、それぞれソース電極Sおよびバックゲート電極BGが接続される。
このNMOSトランジスタでは、出力端子に正の静電気サージが印加されると、寄生抵抗成分13を有するN+型ドレイン領域2をゲート電極6に向けて電流が流れ、これによって、VPNPトランジスタ11のエミッタ−ベース間に電位差VEBが生じる。そして、このエミッタ−ベース間の電位差VEBが所定の電位差VF以上であれば、VPNPトランジスタ11が導通状態になり、その結果、NPN寄生トランジスタ12が導通状態になって、出力端子に印加される正の静電気サージをグランドに逃がすことができる。VPNPトランジスタ11のエミッタ−ベース間に生じる電位差VEBは、寄生抵抗成分13の抵抗値によって制御できるので、この寄生抵抗成分13が適当な抵抗値を有していれば、出力端子に正の静電気サージが印加されたときに、VPNPトランジスタ11を確実に導通状態にすることができ、NMOSトランジスタのドレイン−ゲート間またはドレイン−ソース間の破壊を回避することができる。
また、この発明は、NMOSトランジスタに限らず、N型ウエル領域またはN型半導体基板の表層部に、P+型ドレイン領域およびP+型ソース領域を有するPMOSトランジスタに適用することもできる。この場合、P+型ドレイン領域内に、P型ベース領域がその周辺に形成され、そのP型ベース領域内において、その表層部に、複数のN+型エミッタ領域が互いにほぼ等間隔を空けて形成されるとよい。そして、互いに隣り合うN+型エミッタ領域およびそれらの間のP+型ドレイン領域上に、これらの領域を共通に接続するための帯状のドレインコンタクトが形成されるとよい。この場合、寄生ダイオードを通して、ドレインコンタクトに印加される正の静電気サージを逃がすことができ、VNPNトランジスタおよび寄生PNPトランジスタを通して、ドレインコンタクトに印加される負の静電気サージを逃がすことができる。
2 N+型ドレイン領域
3 N+型ソース領域
4 P+型不純物拡散領域
6 ゲート電極
7 N型ベース領域
8 P+型エミッタ領域
9 ドレインコンタクト
11 VPNPトランジスタ
12 NPN寄生トランジスタ
13 寄生抵抗成分
14 寄生抵抗成分
Claims (2)
- 第1導電型領域と、
この第1導電型領域の表層部に形成された第2導電型ドレイン領域と、
上記第1導電型領域の表層部において上記第2導電型ドレイン領域との間にチャネル領域を隔てて形成された第2導電型ソース領域と、
上記チャネル領域上に形成されたゲート電極と、
平面視において上記第2導電型ドレイン領域の内側に形成された第2導電型ベース領域と、
この第2導電型ベース領域内の表層部において所定方向に互いに間隔を空けて形成された複数の第1導電型エミッタ領域と、
互いに隣り合う第1導電型エミッタ領域と当該第1導電型エミッタ領域間の上記第2導電型ドレイン領域とに跨って接続されたドレインコンタクトとを含み、
上記第2導電型ベース領域は、上記第2導電型ドレイン領域よりも第2導電型不純物の濃度が低く、上記チャネル領域に対して間隔を空けて、上記第2導電型ドレイン領域よりも深く掘り下がって形成されていることを特徴とするMOSトランジスタ。 - 入力端子または出力端子を有する入出力回路に、請求項1に記載のMOSトランジスタが備えられていることを特徴とする半導体集積回路装置。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004136572A JP4197660B2 (ja) | 2004-04-30 | 2004-04-30 | Mosトランジスタおよびこれを備えた半導体集積回路装置 |
CNB2005100677696A CN100487914C (zh) | 2004-04-30 | 2005-04-26 | Mos晶体管以及具备该晶体管的半导体集成电路装置 |
US11/116,357 US7521747B2 (en) | 2004-04-30 | 2005-04-28 | Vertical transistor and a semiconductor integrated circuit apparatus having the same |
KR1020050035914A KR101119859B1 (ko) | 2004-04-30 | 2005-04-29 | Mos 트랜지스터 및 이를 구비한 반도체 집적회로 장치 |
TW094113949A TWI368323B (en) | 2004-04-30 | 2005-04-29 | Mos transistor and a semiconductor integrated circuit apparatus having the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004136572A JP4197660B2 (ja) | 2004-04-30 | 2004-04-30 | Mosトランジスタおよびこれを備えた半導体集積回路装置 |
Publications (2)
Publication Number | Publication Date |
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JP2005317874A JP2005317874A (ja) | 2005-11-10 |
JP4197660B2 true JP4197660B2 (ja) | 2008-12-17 |
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Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004136572A Expired - Lifetime JP4197660B2 (ja) | 2004-04-30 | 2004-04-30 | Mosトランジスタおよびこれを備えた半導体集積回路装置 |
Country Status (5)
Country | Link |
---|---|
US (1) | US7521747B2 (ja) |
JP (1) | JP4197660B2 (ja) |
KR (1) | KR101119859B1 (ja) |
CN (1) | CN100487914C (ja) |
TW (1) | TWI368323B (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102006028721B3 (de) * | 2006-06-20 | 2007-11-29 | Atmel Germany Gmbh | Halbleiterschutzstruktur für eine elektrostatische Entladung |
JP5360460B2 (ja) * | 2007-10-10 | 2013-12-04 | ソニー株式会社 | 静電保護回路 |
US20130087828A1 (en) * | 2010-06-21 | 2013-04-11 | Renesas Electronics Corporation | Semiconductor device and method for manufacturing same |
TWI550818B (zh) * | 2013-08-09 | 2016-09-21 | 天鈺科技股份有限公司 | 靜電防護元件及其製造方法 |
CN104733508B (zh) * | 2013-12-18 | 2018-04-20 | 比亚迪股份有限公司 | 带静电保护结构的mosfet及其制备方法 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4783694A (en) * | 1984-03-16 | 1988-11-08 | Motorola Inc. | Integrated bipolar-MOS semiconductor device with common collector and drain |
US5155562A (en) * | 1990-02-14 | 1992-10-13 | Fuji Electric Co., Ltd. | Semiconductor device equipped with a conductivity modulation misfet |
US5369041A (en) | 1993-07-14 | 1994-11-29 | Texas Instruments Incorporated | Method for forming a silicon controlled rectifier |
JPH0936357A (ja) | 1995-07-18 | 1997-02-07 | Matsushita Electric Ind Co Ltd | 半導体装置 |
KR100200352B1 (ko) | 1995-12-30 | 1999-06-15 | 윤종용 | 반도체 장치의 보호 소자 |
KR100235628B1 (ko) * | 1997-06-25 | 1999-12-15 | 김영환 | 반도체 소자의 제조방법 |
JP3204168B2 (ja) | 1997-07-22 | 2001-09-04 | セイコーエプソン株式会社 | 半導体集積回路 |
JP4357127B2 (ja) | 2000-03-03 | 2009-11-04 | 株式会社東芝 | 半導体装置 |
JP3824310B2 (ja) | 2002-01-18 | 2006-09-20 | ローム株式会社 | 二重拡散型mosfetおよびこれを用いた半導体装置 |
JP3753692B2 (ja) | 2002-12-20 | 2006-03-08 | ローム株式会社 | オープンドレイン用mosfet及びこれを用いた半導体集積回路装置 |
US6949806B2 (en) * | 2003-10-16 | 2005-09-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrostatic discharge protection structure for deep sub-micron gate oxide |
-
2004
- 2004-04-30 JP JP2004136572A patent/JP4197660B2/ja not_active Expired - Lifetime
-
2005
- 2005-04-26 CN CNB2005100677696A patent/CN100487914C/zh active Active
- 2005-04-28 US US11/116,357 patent/US7521747B2/en active Active
- 2005-04-29 KR KR1020050035914A patent/KR101119859B1/ko active IP Right Grant
- 2005-04-29 TW TW094113949A patent/TWI368323B/zh active
Also Published As
Publication number | Publication date |
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JP2005317874A (ja) | 2005-11-10 |
TWI368323B (en) | 2012-07-11 |
TW200610151A (en) | 2006-03-16 |
KR20060047626A (ko) | 2006-05-18 |
CN1694264A (zh) | 2005-11-09 |
US20050253174A1 (en) | 2005-11-17 |
US7521747B2 (en) | 2009-04-21 |
KR101119859B1 (ko) | 2012-02-22 |
CN100487914C (zh) | 2009-05-13 |
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