JP4162076B2 - 半導体記憶装置 - Google Patents

半導体記憶装置 Download PDF

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Publication number
JP4162076B2
JP4162076B2 JP2002156646A JP2002156646A JP4162076B2 JP 4162076 B2 JP4162076 B2 JP 4162076B2 JP 2002156646 A JP2002156646 A JP 2002156646A JP 2002156646 A JP2002156646 A JP 2002156646A JP 4162076 B2 JP4162076 B2 JP 4162076B2
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JP
Japan
Prior art keywords
circuit
power supply
voltage
channel mos
mos transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2002156646A
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English (en)
Japanese (ja)
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JP2004005777A (ja
JP2004005777A5 (enExample
Inventor
雅直 山岡
健一 長田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP2002156646A priority Critical patent/JP4162076B2/ja
Priority to US10/445,919 priority patent/US6862227B2/en
Publication of JP2004005777A publication Critical patent/JP2004005777A/ja
Priority to US11/049,243 priority patent/US6954396B2/en
Priority to US11/204,024 priority patent/US7333385B2/en
Publication of JP2004005777A5 publication Critical patent/JP2004005777A5/ja
Priority to US12/003,970 priority patent/US7920438B2/en
Application granted granted Critical
Publication of JP4162076B2 publication Critical patent/JP4162076B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/021—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in voltage or current generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • G11C5/146—Substrate bias generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0409—Online test

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Static Random-Access Memory (AREA)
JP2002156646A 2002-05-30 2002-05-30 半導体記憶装置 Expired - Lifetime JP4162076B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2002156646A JP4162076B2 (ja) 2002-05-30 2002-05-30 半導体記憶装置
US10/445,919 US6862227B2 (en) 2002-05-30 2003-05-28 Semiconductor memory device having the operating voltage of the memory cell controlled
US11/049,243 US6954396B2 (en) 2002-05-30 2005-02-03 Semiconductor memory device having the operating voltage of the memory cell controlled
US11/204,024 US7333385B2 (en) 2002-05-30 2005-08-16 Semiconductor memory device having the operating voltage of the memory cell controlled
US12/003,970 US7920438B2 (en) 2002-05-30 2008-01-04 Semiconductor memory device having the operating voltage of the memory cell controlled

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002156646A JP4162076B2 (ja) 2002-05-30 2002-05-30 半導体記憶装置

Publications (3)

Publication Number Publication Date
JP2004005777A JP2004005777A (ja) 2004-01-08
JP2004005777A5 JP2004005777A5 (enExample) 2005-10-06
JP4162076B2 true JP4162076B2 (ja) 2008-10-08

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002156646A Expired - Lifetime JP4162076B2 (ja) 2002-05-30 2002-05-30 半導体記憶装置

Country Status (2)

Country Link
US (4) US6862227B2 (enExample)
JP (1) JP4162076B2 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9595307B2 (en) 2014-05-22 2017-03-14 Samsung Electronics Co., Ltd. Volatile memory device and system-on-chip including the same

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JP4162076B2 (ja) * 2002-05-30 2008-10-08 株式会社ルネサステクノロジ 半導体記憶装置
AU2003253205A1 (en) * 2002-09-02 2004-03-19 Koninklijke Philips Electronics N.V. Device writing to a plurality of rows in a memory matrix simultaneously
JP4290457B2 (ja) * 2003-03-31 2009-07-08 株式会社ルネサステクノロジ 半導体記憶装置
US9414777B2 (en) * 2004-07-13 2016-08-16 Dexcom, Inc. Transcutaneous analyte sensor
FR2877143A1 (fr) * 2004-10-25 2006-04-28 St Microelectronics Sa Cellule de memoire volatile preenregistree
US7085175B2 (en) * 2004-11-18 2006-08-01 Freescale Semiconductor, Inc. Word line driver circuit for a static random access memory and method therefor
US7394708B1 (en) * 2005-03-18 2008-07-01 Xilinx, Inc. Adjustable global tap voltage to improve memory cell yield
US7099230B1 (en) * 2005-04-15 2006-08-29 Texas Instruments Incorporated Virtual ground circuit for reducing SRAM standby power
US20060259840A1 (en) * 2005-05-12 2006-11-16 International Business Machines Corporation Self-test circuitry to determine minimum operating voltage
JP4917767B2 (ja) * 2005-07-01 2012-04-18 パナソニック株式会社 半導体記憶装置
WO2007037496A1 (ja) * 2005-09-27 2007-04-05 Nec Corporation 半導体記憶装置及びその電源制御方法
JP4822791B2 (ja) * 2005-10-04 2011-11-24 ルネサスエレクトロニクス株式会社 半導体記憶装置
FR2895556A1 (fr) * 2005-12-26 2007-06-29 St Microelectronics Sa Dispositif de stockage d'informations a memoires sram et procede de mise en oeuvre
JP4865360B2 (ja) * 2006-03-01 2012-02-01 パナソニック株式会社 半導体記憶装置
JP2007328900A (ja) * 2006-05-09 2007-12-20 Matsushita Electric Ind Co Ltd スタティック型半導体記憶装置
US20070286745A1 (en) * 2006-06-09 2007-12-13 Maynard Chance Integrated mixing pump
US7512908B2 (en) * 2006-06-09 2009-03-31 International Business Machines Corporation Method and apparatus for improving SRAM cell stability by using boosted word lines
US7292485B1 (en) 2006-07-31 2007-11-06 Freescale Semiconductor, Inc. SRAM having variable power supply and method therefor
US7679947B2 (en) * 2006-08-02 2010-03-16 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices with source and bulk coupled to separate voltage supplies
JP2008103028A (ja) * 2006-10-19 2008-05-01 Matsushita Electric Ind Co Ltd 半導体記憶装置
JP5057757B2 (ja) 2006-11-30 2012-10-24 株式会社東芝 半導体集積回路
JP5057430B2 (ja) 2006-12-18 2012-10-24 ルネサスエレクトロニクス株式会社 半導体集積回路とその製造方法
EP1953762B1 (en) * 2007-01-25 2013-09-18 Imec Memory device with reduced standby power consumption and method for operating same
US8705300B1 (en) * 2007-02-27 2014-04-22 Altera Corporation Memory array circuitry with stability enhancement features
US7616509B2 (en) * 2007-07-13 2009-11-10 Freescale Semiconductor, Inc. Dynamic voltage adjustment for memory
US8099688B2 (en) * 2007-11-19 2012-01-17 International Business Machines Corporation Circuit design
US7864600B2 (en) * 2008-06-19 2011-01-04 Texas Instruments Incorporated Memory cell employing reduced voltage
US8315117B2 (en) * 2009-03-31 2012-11-20 Freescale Semiconductor, Inc. Integrated circuit memory having assisted access and method therefor
US8379466B2 (en) 2009-03-31 2013-02-19 Freescale Semiconductor, Inc. Integrated circuit having an embedded memory and method for testing the memory
US8634263B2 (en) * 2009-04-30 2014-01-21 Freescale Semiconductor, Inc. Integrated circuit having memory repair information storage and method therefor
CN102460583A (zh) * 2009-06-12 2012-05-16 株式会社半导体理工学研究中心 锁存电路的电压特性调整方法和半导体器件的电压特性调整方法以及锁存电路的电压特性调整器
JP2011054255A (ja) * 2009-09-04 2011-03-17 Panasonic Corp 半導体集積回路
JP5395009B2 (ja) * 2010-07-30 2014-01-22 株式会社半導体理工学研究センター サブスレッショルドｓｒａｍのための電源電圧制御回路及び制御方法
US8811068B1 (en) 2011-05-13 2014-08-19 Suvolta, Inc. Integrated circuit devices and methods
US8467233B2 (en) * 2011-06-06 2013-06-18 Texas Instruments Incorporated Asymmetric static random access memory cell with dual stress liner
US8819603B1 (en) 2011-12-15 2014-08-26 Suvolta, Inc. Memory circuits and methods of making and designing the same
KR102275497B1 (ko) 2014-10-20 2021-07-09 삼성전자주식회사 전원 경로 제어기를 포함하는 시스템 온 칩 및 전자 기기
JP2018010707A (ja) * 2016-07-12 2018-01-18 ルネサスエレクトロニクス株式会社 半導体装置
JP7195133B2 (ja) * 2018-12-19 2022-12-23 ルネサスエレクトロニクス株式会社 半導体装置
CN109785884A (zh) * 2019-01-15 2019-05-21 上海华虹宏力半导体制造有限公司 静态随机存取存储器存储单元
JP2020149746A (ja) * 2019-03-14 2020-09-17 キオクシア株式会社 半導体記憶装置
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9595307B2 (en) 2014-05-22 2017-03-14 Samsung Electronics Co., Ltd. Volatile memory device and system-on-chip including the same
US10236056B2 (en) 2014-05-22 2019-03-19 Samsung Electronics Co., Ltd. Volatile memory device and system-on-chip including the same

Also Published As

Publication number Publication date
US6954396B2 (en) 2005-10-11
JP2004005777A (ja) 2004-01-08
US7920438B2 (en) 2011-04-05
US20050141289A1 (en) 2005-06-30
US20060034143A1 (en) 2006-02-16
US20080117692A1 (en) 2008-05-22
US7333385B2 (en) 2008-02-19
US20030223276A1 (en) 2003-12-04
US6862227B2 (en) 2005-03-01

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