JP3666594B2 - パッケージ型電子部品におけるリード端子の切断方法 - Google Patents

パッケージ型電子部品におけるリード端子の切断方法 Download PDF

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Publication number
JP3666594B2
JP3666594B2 JP2002302984A JP2002302984A JP3666594B2 JP 3666594 B2 JP3666594 B2 JP 3666594B2 JP 2002302984 A JP2002302984 A JP 2002302984A JP 2002302984 A JP2002302984 A JP 2002302984A JP 3666594 B2 JP3666594 B2 JP 3666594B2
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JP
Japan
Prior art keywords
lead terminal
cutting
notch
lead
electronic component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2002302984A
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English (en)
Japanese (ja)
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JP2004140156A (ja
Inventor
正彦 小早川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
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Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP2002302984A priority Critical patent/JP3666594B2/ja
Priority to KR1020057006634A priority patent/KR101090259B1/ko
Priority to AU2003273038A priority patent/AU2003273038A1/en
Priority to PCT/JP2003/013287 priority patent/WO2004036647A1/ja
Priority to US10/531,355 priority patent/US7364947B2/en
Priority to CNB2003801013140A priority patent/CN100382297C/zh
Publication of JP2004140156A publication Critical patent/JP2004140156A/ja
Application granted granted Critical
Publication of JP3666594B2 publication Critical patent/JP3666594B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49548Cross section geometry
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4821Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4842Mechanical treatment, e.g. punching, cutting, deforming, cold welding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP2002302984A 2002-10-17 2002-10-17 パッケージ型電子部品におけるリード端子の切断方法 Expired - Lifetime JP3666594B2 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2002302984A JP3666594B2 (ja) 2002-10-17 2002-10-17 パッケージ型電子部品におけるリード端子の切断方法
KR1020057006634A KR101090259B1 (ko) 2002-10-17 2003-10-17 패키지형 전자부품에 있어서의 리드 단자의 절단 방법
AU2003273038A AU2003273038A1 (en) 2002-10-17 2003-10-17 Method for cutting lead terminal of package type electronic component
PCT/JP2003/013287 WO2004036647A1 (ja) 2002-10-17 2003-10-17 パッケージ型電子部品におけるリード端子の切断方法
US10/531,355 US7364947B2 (en) 2002-10-17 2003-10-17 Method for cutting lead terminal of package type electronic component
CNB2003801013140A CN100382297C (zh) 2002-10-17 2003-10-17 装填型电子部件的引线端子的切断方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002302984A JP3666594B2 (ja) 2002-10-17 2002-10-17 パッケージ型電子部品におけるリード端子の切断方法

Publications (2)

Publication Number Publication Date
JP2004140156A JP2004140156A (ja) 2004-05-13
JP3666594B2 true JP3666594B2 (ja) 2005-06-29

Family

ID=32105062

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002302984A Expired - Lifetime JP3666594B2 (ja) 2002-10-17 2002-10-17 パッケージ型電子部品におけるリード端子の切断方法

Country Status (6)

Country Link
US (1) US7364947B2 (ko)
JP (1) JP3666594B2 (ko)
KR (1) KR101090259B1 (ko)
CN (1) CN100382297C (ko)
AU (1) AU2003273038A1 (ko)
WO (1) WO2004036647A1 (ko)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080210065A1 (en) * 2005-01-21 2008-09-04 Rohm Co., Ltd. Method For Cutting Lead Terminal Of Packaged Electronic Component
JP2008117793A (ja) * 2005-01-21 2008-05-22 Rohm Co Ltd パッケージ型電子部品におけるリード端子の切断方法
JP2006294857A (ja) * 2005-04-11 2006-10-26 Sharp Corp リードフレーム、半導体装置、半導体装置の製造方法および射出成型用金型
JP2008218525A (ja) * 2007-02-28 2008-09-18 Sanyo Electric Co Ltd 導電部材の切断方法および回路装置の製造方法
JP5217800B2 (ja) 2008-09-03 2013-06-19 日亜化学工業株式会社 発光装置、樹脂パッケージ、樹脂成形体並びにこれらの製造方法
JP5755186B2 (ja) * 2012-06-25 2015-07-29 三菱電機株式会社 半導体装置の製造方法および半導体装置
US10074585B2 (en) * 2015-01-20 2018-09-11 Mitsubishi Electric Corporation Power module with dummy terminal structure

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4862246A (en) * 1984-09-26 1989-08-29 Hitachi, Ltd. Semiconductor device lead frame with etched through holes
JPH01220466A (ja) * 1988-02-26 1989-09-04 Mitsui High Tec Inc リードフレーム及び該リードフレームを使った半導体装置の製造方法
JPH0821670B2 (ja) 1990-02-27 1996-03-04 ローム株式会社 合成樹脂封止型電子部品
US5391439A (en) * 1990-09-27 1995-02-21 Dai Nippon Printing Co., Ltd. Leadframe adapted to support semiconductor elements
JP3008470B2 (ja) 1990-09-27 2000-02-14 大日本印刷株式会社 リードフレーム
JP2583353B2 (ja) 1990-11-05 1997-02-19 九州日本電気株式会社 半導体装置用リードフレーム
JPH051246U (ja) * 1991-06-21 1993-01-08 山形日本電気株式会社 表面実装型半導体装置用リードフレーム
JPH051246A (ja) 1991-06-26 1993-01-08 Showa Highpolymer Co Ltd 防汚塗料組成物
JPH0555436A (ja) 1991-08-28 1993-03-05 Nec Corp 半導体装置用リードフレーム
JP3275413B2 (ja) 1993-01-21 2002-04-15 凸版印刷株式会社 リードフレームおよびその製造方法
US5647124A (en) * 1994-04-25 1997-07-15 Texas Instruments Incorporated Method of attachment of a semiconductor slotted lead to a substrate
JP3257904B2 (ja) * 1994-08-11 2002-02-18 新光電気工業株式会社 リードフレームとその製造方法
JPH11260981A (ja) * 1998-03-13 1999-09-24 Matsushita Electric Works Ltd リードフレームの製造方法
JPH11354705A (ja) * 1998-06-04 1999-12-24 Toshiba Corp 半導体装置及び半導体装置の製造方法
US6498099B1 (en) * 1998-06-10 2002-12-24 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation
JP2000114426A (ja) * 1998-10-07 2000-04-21 Mitsui High Tec Inc 片面樹脂封止型半導体装置
US6399415B1 (en) * 2000-03-20 2002-06-04 National Semiconductor Corporation Electrical isolation in panels of leadless IC packages
US6452255B1 (en) * 2000-03-20 2002-09-17 National Semiconductor, Corp. Low inductance leadless package
US6355502B1 (en) * 2000-04-25 2002-03-12 National Science Council Semiconductor package and method for making the same
JP2001320007A (ja) * 2000-05-09 2001-11-16 Dainippon Printing Co Ltd 樹脂封止型半導体装置用フレーム
US6483178B1 (en) * 2000-07-14 2002-11-19 Siliconware Precision Industries Co., Ltd. Semiconductor device package structure
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US6812552B2 (en) * 2002-04-29 2004-11-02 Advanced Interconnect Technologies Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging

Also Published As

Publication number Publication date
AU2003273038A1 (en) 2004-05-04
CN100382297C (zh) 2008-04-16
US20060141672A1 (en) 2006-06-29
KR101090259B1 (ko) 2011-12-06
JP2004140156A (ja) 2004-05-13
KR20050053777A (ko) 2005-06-08
CN1703777A (zh) 2005-11-30
WO2004036647A1 (ja) 2004-04-29
US7364947B2 (en) 2008-04-29

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