JP2697406B2 - 多重クロック・サイクルを持つサブレンジ型アナログ・デジタル変換器 - Google Patents

多重クロック・サイクルを持つサブレンジ型アナログ・デジタル変換器

Info

Publication number
JP2697406B2
JP2697406B2 JP3254146A JP25414691A JP2697406B2 JP 2697406 B2 JP2697406 B2 JP 2697406B2 JP 3254146 A JP3254146 A JP 3254146A JP 25414691 A JP25414691 A JP 25414691A JP 2697406 B2 JP2697406 B2 JP 2697406B2
Authority
JP
Japan
Prior art keywords
voltage
ladder
group
coarse
fine
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP3254146A
Other languages
English (en)
Japanese (ja)
Other versions
JPH04282919A (ja
Inventor
裕一 中谷
博則 三宅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Solutions Inc
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Solutions Inc, Motorola Inc filed Critical Motorola Solutions Inc
Publication of JPH04282919A publication Critical patent/JPH04282919A/ja
Application granted granted Critical
Publication of JP2697406B2 publication Critical patent/JP2697406B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H03M1/0675—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy
    • H03M1/069—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy by range overlap between successive stages or steps
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/1205—Multiplexed conversion systems
    • H03M1/121—Interleaved, i.e. using multiple converters or converter parts for one channel
    • H03M1/1215—Interleaved, i.e. using multiple converters or converter parts for one channel using time-division multiplexing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
    • H03M1/142—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit the reference generators for the steps being arranged in a common two-dimensional array
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
    • H03M1/144—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit the steps being performed sequentially in a single stage, i.e. recirculation type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
    • H03M1/145—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit the steps being performed sequentially in series-connected stages
    • H03M1/146—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit the steps being performed sequentially in series-connected stages all stages being simultaneous converters

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)
JP3254146A 1990-09-17 1991-09-06 多重クロック・サイクルを持つサブレンジ型アナログ・デジタル変換器 Expired - Fee Related JP2697406B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/583,632 US5099240A (en) 1990-09-17 1990-09-17 Subranging adc with error correction through increased fine step span and noise reducing layout
US583632 1990-09-17

Publications (2)

Publication Number Publication Date
JPH04282919A JPH04282919A (ja) 1992-10-08
JP2697406B2 true JP2697406B2 (ja) 1998-01-14

Family

ID=24333940

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3254146A Expired - Fee Related JP2697406B2 (ja) 1990-09-17 1991-09-06 多重クロック・サイクルを持つサブレンジ型アナログ・デジタル変換器

Country Status (4)

Country Link
US (1) US5099240A (en:Method)
EP (1) EP0481190B1 (en:Method)
JP (1) JP2697406B2 (en:Method)
DE (1) DE69130699T2 (en:Method)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0522136A (ja) * 1990-11-16 1993-01-29 Hitachi Ltd アナログ／デイジタル変換器
JP3107231B2 (ja) * 1991-02-22 2000-11-06 ソニー株式会社 アナログデイジタル変換回路
JPH05300020A (ja) * 1992-04-17 1993-11-12 Mitsubishi Electric Corp 直並列型ａ／ｄ変換器
US5296858A (en) * 1992-05-14 1994-03-22 Advanced Micro Devices, Inc. Improved two-stage analog-to-digital converter
US5341137A (en) * 1992-11-06 1994-08-23 National Semiconductor Corporation Analog to digital converter using parallel folder and decoder circuits
US5552784A (en) * 1994-06-30 1996-09-03 Northrop Grumman Corporation Distortion reduction circuit for analog to digital converter system
US5726653A (en) * 1996-01-22 1998-03-10 Industrial Technology Research Institute Tri-step analog-to-digital converter
JP3597636B2 (ja) * 1996-05-07 2004-12-08 株式会社ルネサステクノロジ サブレンジング型ａ／ｄ変換器
JPH1013229A (ja) * 1996-06-20 1998-01-16 Toshiba Ave Corp 直並列型ａ／ｄ変換器
US5973632A (en) * 1998-03-03 1999-10-26 Powerchip Semiconductor Corp. Sub-range flash analog-to-digital converter
JP3887489B2 (ja) * 1998-06-16 2007-02-28 富士通株式会社 基準電圧発生回路
US6246352B1 (en) * 1999-07-30 2001-06-12 Texas Instruments Incorporated Analog-to-digital converter with flush access to digital-to-analog resistor string
US6459394B1 (en) * 2001-05-22 2002-10-01 Cirrus Logic, Inc. Multi-bank flash ADC array with uninterrupted operation during offset calibration and auto-zero
JP3618689B2 (ja) * 2001-05-31 2005-02-09 イノテック株式会社 チョッパ型電圧比較器及びそれを用いたアナログデジタル変換器
US6496133B1 (en) * 2001-07-11 2002-12-17 Texas Instruments Incorporated Resistor string integrated circuit and method for reduced linearity error
US6714886B2 (en) * 2002-02-13 2004-03-30 Eric C. Sung System and method of DC calibration of amplifiers
US6570523B1 (en) * 2002-02-13 2003-05-27 Intersil Americas Inc. Analog to digital converter using subranging and interpolation
JP2004289759A (ja) * 2003-03-25 2004-10-14 Rohm Co Ltd Ａ／ｄ変換器
US6999019B2 (en) * 2004-04-08 2006-02-14 The Boeing Company Subranging analog-to-digital converter with integrating sample-and-hold
US7116260B2 (en) * 2005-01-26 2006-10-03 Raytheon Company Mismatch shaped analog to digital converter
US8049652B2 (en) * 2009-01-20 2011-11-01 Marvell International Ltd. Reference pre-charging for two-step subranging ADC architecture
TWI452846B (zh) * 2010-12-16 2014-09-11 Univ Nat Cheng Kung 分段式類比數位轉換器及其方法
TWI462487B (zh) * 2011-12-23 2014-11-21 Ind Tech Res Inst 類比數位轉換裝置及其轉換方法
KR20220159840A (ko) * 2021-05-26 2022-12-05 에스케이하이닉스 주식회사 전자 장치 및 그 동작 방법

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS589426A (ja) * 1981-07-10 1983-01-19 Sony Corp Ａ／ｄコンバ−タ
AU557017B2 (en) * 1981-07-21 1986-12-04 Sony Corporation Analog-to-digital converter
JPS58107720A (ja) * 1981-12-22 1983-06-27 Sony Corp Ａ／ｄコンバ−タ
JPS61120530A (ja) * 1984-11-15 1986-06-07 Toshiba Corp アナログ・デジタル変換器
US4612531A (en) * 1985-02-12 1986-09-16 Rca Corporation Intermeshed resistor network for analog to digital conversion
US4745393A (en) * 1985-09-25 1988-05-17 Hitachi, Ltd Analog-to-digital converter
JPS62245722A (ja) * 1986-04-18 1987-10-27 Hitachi Ltd 直並列形ａ／ｄ変換器
US4733217A (en) * 1986-05-08 1988-03-22 Rca Corporation Subranging analog to digital converter
GB2199710A (en) * 1986-12-23 1988-07-13 Philips Electronic Associated Analogue to digital converter
JPS63299615A (ja) * 1987-05-29 1988-12-07 Nec Corp 直並列型ａ／ｄ変換器
JPH01106526A (ja) * 1987-10-19 1989-04-24 Mitsubishi Electric Corp Ａｄ変換器
JPH01191520A (ja) * 1988-01-27 1989-08-01 Sony Corp Ａｄ変換回路
JPH0277931U (en:Method) * 1988-12-02 1990-06-14

Also Published As

Publication number Publication date
EP0481190A2 (en) 1992-04-22
US5099240A (en) 1992-03-24
EP0481190A3 (en:Method) 1994-03-02
DE69130699D1 (de) 1999-02-11
EP0481190B1 (en) 1998-12-30
DE69130699T2 (de) 1999-07-22
JPH04282919A (ja) 1992-10-08

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