JP2666788B2 - チップサイズ半導体装置の製造方法 - Google Patents
チップサイズ半導体装置の製造方法Info
- Publication number
- JP2666788B2 JP2666788B2 JP7271449A JP27144995A JP2666788B2 JP 2666788 B2 JP2666788 B2 JP 2666788B2 JP 7271449 A JP7271449 A JP 7271449A JP 27144995 A JP27144995 A JP 27144995A JP 2666788 B2 JP2666788 B2 JP 2666788B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- carrier tape
- chip
- manufacturing
- adhesive film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 138
- 238000004519 manufacturing process Methods 0.000 title claims description 23
- 239000002313 adhesive film Substances 0.000 claims description 58
- 238000005520 cutting process Methods 0.000 claims description 28
- 238000000034 method Methods 0.000 claims description 28
- 239000011347 resin Substances 0.000 claims description 27
- 229920005989 resin Polymers 0.000 claims description 27
- 239000002184 metal Substances 0.000 claims description 24
- 229910052751 metal Inorganic materials 0.000 claims description 24
- 238000010438 heat treatment Methods 0.000 claims description 16
- 238000007650 screen-printing Methods 0.000 claims description 5
- 238000004080 punching Methods 0.000 claims description 4
- 238000003860 storage Methods 0.000 claims description 3
- 239000000853 adhesive Substances 0.000 claims 2
- 230000001070 adhesive effect Effects 0.000 claims 2
- 238000007789 sealing Methods 0.000 description 13
- 210000000078 claw Anatomy 0.000 description 10
- 238000010586 diagram Methods 0.000 description 8
- 238000007796 conventional method Methods 0.000 description 4
- 238000012546 transfer Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 230000035882 stress Effects 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 239000012050 conventional carrier Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000011888 foil Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000001105 regulatory effect Effects 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 239000004809 Teflon Substances 0.000 description 1
- 229920006362 Teflon® Polymers 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010330 laser marking Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/86—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using tape automated bonding [TAB]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01039—Yttrium [Y]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7271449A JP2666788B2 (ja) | 1995-10-19 | 1995-10-19 | チップサイズ半導体装置の製造方法 |
| US08/733,207 US5759873A (en) | 1995-10-19 | 1996-10-17 | Method of manufacturing chip-size package-type semiconductor device |
| EP96116769A EP0769812A3 (en) | 1995-10-19 | 1996-10-18 | Method of manufacturing chip-size package-type semiconductor device |
| CN96121929A CN1107972C (zh) | 1995-10-19 | 1996-10-19 | 按芯片尺寸封装型半导体器件的制造方法 |
| KR1019960046982A KR100203603B1 (ko) | 1995-10-19 | 1996-10-19 | 칩 크기의 패키지형 반도체 장치의 제조 방법 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7271449A JP2666788B2 (ja) | 1995-10-19 | 1995-10-19 | チップサイズ半導体装置の製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09115950A JPH09115950A (ja) | 1997-05-02 |
| JP2666788B2 true JP2666788B2 (ja) | 1997-10-22 |
Family
ID=17500189
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7271449A Expired - Fee Related JP2666788B2 (ja) | 1995-10-19 | 1995-10-19 | チップサイズ半導体装置の製造方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US5759873A (zh) |
| EP (1) | EP0769812A3 (zh) |
| JP (1) | JP2666788B2 (zh) |
| KR (1) | KR100203603B1 (zh) |
| CN (1) | CN1107972C (zh) |
Families Citing this family (31)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW281795B (zh) * | 1994-11-30 | 1996-07-21 | Sharp Kk | |
| KR100186333B1 (ko) * | 1996-06-20 | 1999-03-20 | 문정환 | 칩 사이즈 반도체 패키지 및 그 제조방법 |
| DE19800566A1 (de) * | 1998-01-09 | 1999-07-15 | Siemens Ag | Verfahren zum Herstellen eines Halbleiterbauelementes und ein derart hergestelltes Halbleiterbauelement |
| US6230719B1 (en) * | 1998-02-27 | 2001-05-15 | Micron Technology, Inc. | Apparatus for removing contaminants on electronic devices |
| US5972234A (en) * | 1998-04-06 | 1999-10-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Debris-free wafer marking method |
| KR100556240B1 (ko) * | 1998-07-28 | 2006-03-03 | 세이코 엡슨 가부시키가이샤 | 반도체 장치 제조방법 |
| US6428641B1 (en) * | 1998-08-31 | 2002-08-06 | Amkor Technology, Inc. | Method for laminating circuit pattern tape on semiconductor wafer |
| US6479887B1 (en) | 1998-08-31 | 2002-11-12 | Amkor Technology, Inc. | Circuit pattern tape for wafer-scale production of chip size semiconductor packages |
| JP3816253B2 (ja) * | 1999-01-19 | 2006-08-30 | 富士通株式会社 | 半導体装置の製造方法 |
| JP3504543B2 (ja) | 1999-03-03 | 2004-03-08 | 株式会社日立製作所 | 半導体素子の分離方法およびその装置並びに半導体素子の搭載方法 |
| US6181569B1 (en) | 1999-06-07 | 2001-01-30 | Kishore K. Chakravorty | Low cost chip size package and method of fabricating the same |
| US6210522B1 (en) | 1999-06-15 | 2001-04-03 | Lexmark International, Inc. | Adhesive bonding laminates |
| US6361146B1 (en) | 1999-06-15 | 2002-03-26 | Lexmark International, Inc. | Adhesive bonding laminates |
| US6322903B1 (en) | 1999-12-06 | 2001-11-27 | Tru-Si Technologies, Inc. | Package of integrated circuits and vertical integration |
| JP4128319B2 (ja) * | 1999-12-24 | 2008-07-30 | 株式会社新川 | マルチチップボンディング方法及び装置 |
| CH695407A5 (de) * | 2000-07-03 | 2006-04-28 | Esec Trading Sa | Verfahren und Einrichtung zur Montage von Halbleiterchips auf einem flexiblen Substrat. |
| JP3619773B2 (ja) * | 2000-12-20 | 2005-02-16 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
| TW536768B (en) * | 2001-08-03 | 2003-06-11 | Matsushita Electric Ind Co Ltd | Method for fabricating semiconductor-mounting body and apparatus for fabricating semiconductor-mounting body |
| JP2003330041A (ja) * | 2002-05-10 | 2003-11-19 | Sharp Corp | 半導体装置及びそれを備えた表示パネルモジュール |
| US7416922B2 (en) * | 2003-03-31 | 2008-08-26 | Intel Corporation | Heat sink with preattached thermal interface material and method of making same |
| US6987671B2 (en) * | 2003-06-26 | 2006-01-17 | Intel Corporation | Composite thermal interface devices and methods for integrated circuit heat transfer |
| US7527090B2 (en) * | 2003-06-30 | 2009-05-05 | Intel Corporation | Heat dissipating device with preselected designed interface for thermal interface materials |
| AU2005324288B2 (en) * | 2005-01-10 | 2011-02-17 | Memjet Technology Limited | Inkjet printhead production method |
| JP4975605B2 (ja) * | 2007-12-26 | 2012-07-11 | 東京エレクトロン株式会社 | 処理システム、処理システムの制御方法およびソフトウェアのバージョンアップ方法 |
| JP5557352B2 (ja) * | 2012-04-20 | 2014-07-23 | Ｎｅｃエンジニアリング株式会社 | シート切断装置、チップ製造装置、シート切断方法、チップ製造方法及びシート切断プログラム |
| US10186458B2 (en) * | 2012-07-05 | 2019-01-22 | Infineon Technologies Ag | Component and method of manufacturing a component using an ultrathin carrier |
| US9922935B2 (en) | 2014-09-17 | 2018-03-20 | Samsung Electronics Co., Ltd. | Semiconductor package and method of fabricating the same |
| KR20160032958A (ko) | 2014-09-17 | 2016-03-25 | 삼성전자주식회사 | 반도체 패키지 및 이의 제조 방법 |
| CN104960349B (zh) * | 2015-06-11 | 2021-08-06 | 苏州海博智能系统有限公司 | 一种电子显示屏印刷片材的处理设备 |
| CN104942877B (zh) * | 2015-06-18 | 2021-08-13 | 苏州海博智能系统有限公司 | 一种电子显示屏印刷片材的处理设备 |
| KR102036335B1 (ko) * | 2019-07-09 | 2019-10-24 | (주)에이티에스 | Cof 2중 타발장치 |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60224254A (ja) * | 1984-04-20 | 1985-11-08 | Hitachi Yonezawa Denshi Kk | リ−ドフレ−ム切断方法 |
| US5049434A (en) * | 1984-04-30 | 1991-09-17 | National Starch And Chemical Investment Holding Corporation | Pre-patterned device substrate device-attach adhesive transfer system |
| JPS62111825A (ja) * | 1985-11-06 | 1987-05-22 | Fuji Kikai Seizo Kk | キヤリヤテ−プから電子部品を取り出す方法 |
| JPH0787277B2 (ja) * | 1987-03-25 | 1995-09-20 | ティーディーケイ株式会社 | 表面実装部品の基板搭載方法 |
| JPS6443458A (en) * | 1987-08-11 | 1989-02-15 | Nitto Denko Corp | Stick cutter for tacky tape with respect to thin board |
| JPH03250634A (ja) * | 1990-02-28 | 1991-11-08 | Fujitsu Ltd | 半導体装置の製造方法 |
| JPH06192630A (ja) * | 1992-12-25 | 1994-07-12 | Sony Corp | カード型半導体装置のパネルへの両面接着テープ接着 用セパレータ |
| JP2570123B2 (ja) * | 1993-07-13 | 1997-01-08 | 日本電気株式会社 | 半導体装置及びその製造方法 |
-
1995
- 1995-10-19 JP JP7271449A patent/JP2666788B2/ja not_active Expired - Fee Related
-
1996
- 1996-10-17 US US08/733,207 patent/US5759873A/en not_active Expired - Fee Related
- 1996-10-18 EP EP96116769A patent/EP0769812A3/en not_active Withdrawn
- 1996-10-19 CN CN96121929A patent/CN1107972C/zh not_active Expired - Fee Related
- 1996-10-19 KR KR1019960046982A patent/KR100203603B1/ko not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR970024041A (ko) | 1997-05-30 |
| EP0769812A2 (en) | 1997-04-23 |
| CN1107972C (zh) | 2003-05-07 |
| JPH09115950A (ja) | 1997-05-02 |
| EP0769812A3 (en) | 1998-10-21 |
| CN1155162A (zh) | 1997-07-23 |
| KR100203603B1 (ko) | 1999-07-01 |
| US5759873A (en) | 1998-06-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2666788B2 (ja) | チップサイズ半導体装置の製造方法 | |
| KR100330937B1 (ko) | 복수의 초소형 전자소자를 리드변형을 이용하여 접속하는 방법 및 장치 | |
| US7592690B2 (en) | Semiconductor device including semiconductor elements mounted on base plate | |
| EP0704899A2 (en) | Method of manufacturing chip-size package-type semiconductor device | |
| JP2008544554A (ja) | 薄型可撓性基板を使用するフリップチップダイ組立体 | |
| US20010009376A1 (en) | Probe arrangement assembly, method of manufacturing probe arrangement assembly, probe mounting method using probe arrangement assembly, and probe mounting apparatus | |
| JP2925074B2 (ja) | Ｌｏｃ型半導体チップパッケージ及びその製造方法 | |
| JP2793766B2 (ja) | 導電ペースト転写方法 | |
| US7727861B2 (en) | Method and device for contacting semiconductor chips | |
| JP2000232119A (ja) | 半導体チップの接続部材及びその製造方法とその接続部材を用いた半導体チップの接続方法 | |
| JPH05291260A (ja) | バンプ形成方法 | |
| JP2000022031A (ja) | 導電性ボールの実装方法 | |
| JPH07153764A (ja) | はんだバンプ形成方法 | |
| JP2800806B2 (ja) | 半導体装置及びその製造方法 | |
| JP3019899B2 (ja) | マルチチップモジュールの製造方法 | |
| JPH0964093A (ja) | 電子部品 | |
| JP2553810B2 (ja) | ボンディング装置 | |
| JP2001156111A (ja) | 半導体装置の組立方法 | |
| KR100239182B1 (ko) | 파이롯팅(piloting) 방식을 이용한 리드 프레임의 제조방법 | |
| CN116230649A (zh) | 电子封装模块及其制造方法 | |
| EP0901164A2 (en) | Integrated circuit packaging method, packaging apparatus, and package | |
| JP2000150581A (ja) | 半導体装置およびその製造方法並びにそれに使用されるボンディング装置 | |
| KR20020078600A (ko) | 스크린 인쇄기와 이를 이용한 반도체 패키지의 위치정렬방법 | |
| JP2000349197A (ja) | 半導体ウェハ封止基板 | |
| JPH0362539A (ja) | インナーリードのボンディング装置 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19970527 |
|
| LAPS | Cancellation because of no payment of annual fees |